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Add Wire FPGA to main branch wire #3499
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09d0c92
Added project files
llysdal 7165d89
Added input/outputs and connection drawing (nonfunctional so far)
llysdal 749a32e
Improved connection drawing
llysdal 9d76895
Flipped around connection structure, minor visual improvements
llysdal 52f9fe4
Added nodetypes, with new Input and Output gates
llysdal dbff7d5
Made saving and loading functional
llysdal c034cd6
Fixed bug with tab closing
llysdal 925604f
Fixed bugs related to saving
llysdal 67df135
Added file naming and tab names
llysdal fb8ef9a
Made panel cover much nicer
llysdal 7c95df7
Added uploading FPGA data to FPGA chip
llysdal bf2f2ef
Added node compiling
llysdal 49adf42
Compiler finds IO now, and chip updates its IO
llysdal 4f27162
Refactored mock-gates into real gate component
llysdal fbab475
Added basic FPGA functionality
llysdal b25fe4c
Added todo.txt
llysdal 7dcd5b1
Moved compilation to serverside
llysdal c4acbc5
Improved FPGA entity running
llysdal 9eedd0e
Added ability to create and remove gates (still in development)
llysdal e60b6bc
Fixed net bug where indexes were ignored
llysdal 635d28d
Fixed execution bug regarding outputs
llysdal ba7c9f8
Added type colors
llysdal ddf0e25
Added type checking to editor
llysdal d0c0cfc
Fixed visual bugs and improved colors
llysdal 0556712
Added all input and output gates
llysdal c0fc6d8
Multiple outputs can now be drawn
llysdal 86c9168
Multiple outputs are now evaluated
llysdal 3d21325
Improved execution massively, inputs now get default values, executio…
llysdal 614ed87
Fixed error in last execution upgrade
llysdal f165807
Update todo.txt
llysdal 13f5304
Updated vector io gate names
llysdal 998f61f
Added execution benchmarking
llysdal da2b11d
Timed gates now work, and execution interval is adjustable
llysdal ac7cc47
Added a way to change execution interval in the editor
llysdal d447805
Added input output labels in node editor
llysdal f036e4e
Improved execution
llysdal 3275e95
Fixed node editor related bugs
llysdal a0526bc
Made node grabbing a lot nicer
llysdal 3d84833
Inputs and outputs can now be named in the editor
llysdal 0d66614
Added normal constants, and made them work during execution
llysdal b4da811
Added all constant values
llysdal f0268a3
Added infinite recursion protection
llysdal 9e5d110
Update todo.txt
llysdal fcaf7fb
Attempted to implement "last" gate. all code commented out for future…
llysdal d484dde
Made error messages better
llysdal bdd3ca2
Fixed client overlay
llysdal ff17cbb
Added before-compilation validation on serverside
llysdal 22ef113
Fixed infinite loop detection
llysdal 4b2f843
Added cpu time limits
llysdal 407c3a9
Improved editor node creation a bit
llysdal f1d524b
Update nodeeditor.lua
llysdal 6f44147
Made error handling better
llysdal 0d597eb
Revised input output name delegation
llysdal 4520c7d
Added help text for when there is no nodes
llysdal edfb22a
Improved top bar color a bit
llysdal 9191d22
Update nodeeditor.lua
llysdal 057d90f
Update todo.txt
llysdal c2c0ebc
Apply force gates now work
llysdal bd96ea3
Resetting now removes errors
llysdal 1dabd4f
Added support for compact gates
llysdal a806df4
Chip clears errors on uploads now
llysdal 7895550
Updated todo
llysdal 9fd8320
Added support for duplicating
llysdal 16dc1dd
Fixed bug introduced by last commit
llysdal 61c3814
Improved tickrate detection
llysdal 7e68da9
Use tickrate for lower limit on execution interval
llysdal 2c5e443
Made spike quota optional
llysdal 586d5a5
Updated todo and removed print
llysdal b477549
Added node selection, and selection moving and deleting
llysdal 6e8a1d7
Update todo.txt
llysdal ab7ec60
Added copying and pasting
llysdal 9212c71
Added upload limit
llysdal bf2adb1
Added cool new toolgun screen
llysdal acc1416
Improved error messages
llysdal d765f1c
Added functionality to tool screen
llysdal 4e08dc9
Made small text correction
llysdal 24f53ad
Added first step to have looping
llysdal 33a022a
Update todo.txt
llysdal ec26827
Fixed bug related to re-uploading chips
llysdal a2299c2
Update todo.txt
llysdal 3eba1ba
Removed vector2 and vector4 io gates
llysdal 8fb5dfa
Renamed vector io gates
llysdal dcc2aa5
Renamed vector constant gate
llysdal ea20154
Added in missing execution last gates
llysdal ae4e3a9
Update addon.json
llysdal 401d2b1
Fixed saving bug
llysdal af4d6a1
Updated the limit and added some permission work
llysdal 7e9fa7b
Fixed bug where clients wouldn't create fpgachip dir
llysdal 45388e0
Various tweaks
llysdal 313051a
Removed error message on no code specified
llysdal 8a13319
Added downloading
llysdal 686aa29
Fixed derma changing up order of execution interval and chip name
llysdal be69f15
Update todo.txt
llysdal 6b55960
Fixed bug related to downloading empty chips
llysdal bf89b9f
Made error detection on open better, and made shutdow hook work
llysdal b69bc70
Fixed frame being created on first tab
llysdal 56b5441
Update todo.txt
llysdal 53a22f7
Made copying copy from center
llysdal 20b934a
Fixed bugs related to releasing mouse outside window
llysdal 9be9355
"Banned" string to memory and string from memory
llysdal cbd3811
Renamed highspeed-input to wirelink-input
llysdal 7a65b2c
Updated todo.txt
llysdal 8b9423b
Fixed node pasting bug (non sequential)
llysdal 6db7a42
Better default model
llysdal ce4e951
Made zoom better
llysdal 6cce036
Added logo
llysdal c349965
Fixed for gmad
llysdal 162fb14
Removed unnecessary tool_loader
llysdal 089fb19
QoL tweaks (_helloworld_, default to 0.1 execution interval, check if…
llysdal 11d698a
Fixed whitelist issue
llysdal 2b4a69e
Updated logo
llysdal 3d72c7f
Update logo
llysdal e192da5
Fixed horrible bug that limited executions to 50 cycles
llysdal 5f6f8f4
Fixed bug where you couldn't create new file via filebrowser
llysdal 46a9996
Added colored connections
llysdal d593583
Changed edit behaviour to be more userfriendly
llysdal 3624b53
Added new cpu gates, with some initial conversion gates
llysdal 0d40b8c
Massively improved performance monitoring
llysdal e2c999c
Updated old logo
llysdal 87d234f
Update todo.txt
llysdal 24dc281
Update todo.txt
llysdal 54aac92
Fixed significant bug where you couldn't create/remove nodes after ed…
llysdal 3f28a2a
Update todo.txt
llysdal ac7f014
Removed unnecessary "output" lambda from io gates
llysdal 913fba6
Fixed wiring bug with entities
llysdal 9fb907b
Added constant "self" and "owner" gates
llysdal 478abb6
Added new execution delta gate along with tickrate constant gate
llysdal 72fced0
Implemented postexecution hook, and created "previous" gates
llysdal b2d519b
"Previous" gates can now trigger an execution at next tick
llysdal 1bcb34a
Added ExecuteOn system
llysdal d1f0046
Added node colors
llysdal 38f9d15
Added new FPGA Helper
llysdal f0557f0
Updated node colors to be a bit more subtle
llysdal ac56e6d
Update help.lua
llysdal b8318ca
Update todo.txt
llysdal 07214a5
Fixed bug related to clients not getting help.lua
llysdal c22a9d8
Fixed stupid bug with execute on trigger
llysdal b8af866
Fixed last and previous gate behaviour (postcycle and postexecution)
llysdal 09d6c11
Added new timed last execution gates, and improved Help section
llysdal 3b1aa3d
Made timebench average over a longer period of time - more resistant …
llysdal 6c96e3f
Added logic gates
llysdal 255a0b4
Fixed lua syntax
llysdal 0eb1dbf
Added half/full adders and subtractors
llysdal 8630645
Reworked gate explorer to be able to handle preset order
llysdal c583c4e
Added "wide" logic gates
llysdal 4eb1071
Added 4/8/16 bit adders
llysdal 857c0e5
Added bit_operations gates
llysdal 4179ab6
Temporary fix for unfocus bug
llysdal cc32f9a
Fixed bug where FPGA would cause crash
llysdal ba88bcf
Added global copy / paste buffer
llysdal fe132bc
Fixed bug with extra data not getting copied with nodes
llysdal c95acf2
Added "type annotations" to arithmetic gates
llysdal faeb712
Changed output names of bit operation and logic gates
llysdal 3207a0b
Added new text features for editor
llysdal 4cc41d9
Implemented multi connection drawing
llysdal 67cb887
Added memory gates (register and program counter)
llysdal e383854
Clarified that the program counter is edge triggered
llysdal 666cea1
Fail without errors on missing gates
llysdal b7f5233
Preparation work to add labels and comments
llysdal c4da00d
Added new Editor nodes, in the form of a label and comment gate
llysdal 8581bea
Implemented serverside FPGA code that deals with "visual" nodes
llysdal 439f044
Edited colors to be a bit nicer
llysdal ee483af
Added help for new features
llysdal 32545a5
Fixed error in help text
llysdal eb970d3
Added overlay, which shows status and auxillary info
llysdal 774b03d
Added align to grid functionality
llysdal ba2ad47
Restructued nodeeditor.lua and added sections
llysdal 82bbb67
Minor bugfix
llysdal 4c29092
Edited helloworld a bit, and made fonts nicer in help
llysdal 94f91b7
Fixed error with "new file" button in tool
llysdal cf87595
Added gate searching
llysdal 7ce5c4a
WIP FPGA inside view
llysdal 47561e8
Update README.md
llysdal b134b7a
Improved the inside view - nodes are now drawn correctly
llysdal 3d9ff1c
Made node compilation use local variables.
llysdal 4bd6a57
Added more inside view features
llysdal 1ddbba8
Added time hashing, to only send inside view to clients once
llysdal 441228d
Implemented options syncing, and created option "allow inside view
llysdal 7ef2a78
Removed debug print statement
llysdal 5d02009
Fixed options behaving bad with empty chips
llysdal 4230fe6
Fixed issue relating to edges in inside view
llysdal e9c5d2d
Only draw inside view inside the box, scissor rect the rest
llysdal 9940e8b
Massively decreased net message size for inside views
llysdal c4653fd
Improved runtime error message a bit, adding clarity
llysdal 8c78ba0
Minor design tweak for FPGA Options
llysdal 5f89dcd
Fixed issue where error wouldn't show in overlay
llysdal 72c3203
Update todo.txt
llysdal 85ab7f1
Fixed bug when uploading empty chip
llysdal 6e3ad87
Added new selection gates
llysdal 3f3ee7b
Fixed obscure bug related to FPGA view updating
llysdal 16e4208
Fixed net code usage bug in inside view timer
llysdal 8059da0
Delete todo.txt
llysdal adc5ad0
Create .gitignore
Anticept 29fffcf
Create SECURITY.md
Anticept 712bac5
Create CONTRIBUTING.md
Anticept 8bff1f6
Update addon.json
Anticept d3756df
Update addon.json
Anticept 9432b62
Made node editor use local gate helpers instead of methods
llysdal 36570e4
Moved DefaultValueForType into global shared space
llysdal 41afe40
Made node editor conform to coding style
llysdal aff7714
Refactored various parts of the node editor
llysdal 6f48170
Fixed a function call not working in nodeeditor
llysdal 1512c54
Fixed use of deprecated wirelib function
llysdal 9038b8e
Fixed error when downloading from fpga
llysdal ccc4063
Overhauled upload/download routines to compress data and decompress data
llysdal 3ec6729
Refactored clientside inside view net code
llysdal 06ff71d
Utilize WireLib.ParseEscapes for string constants
Denneisk 3548c44
Fix rebase
llysdal 048b657
fixing whitespace
llysdal 6aea947
Removed unused variables and functions
llysdal 301e8b3
Replace surface.ScreenWidth and ScreenHeight with SrcW and SrcH
llysdal 583cbdb
Replaced deprecated functions with new ones
llysdal 51fd7c6
Fixed inconsistent use of ~!
llysdal 245be3f
Removed empty if statement
llysdal efc137d
Replaced ' ' with " "
llysdal d5ee23d
Removed unnecessary parentheses
llysdal 85ff697
Fixed spelling mistake in Scr
llysdal e8cb623
Removed usages of ~=
llysdal 41be55c
Removed unused variables
llysdal f2730eb
Fixed bug with visual nodes
llysdal 613ee9b
Changed help HTML
llysdal 1d721db
Convert indentation to using tabs
llysdal ac77e64
Merged wire fpga autoload into wire load
llysdal bd15cf1
Removed trailing whitespace
llysdal 0d9959d
Removed personal contact and author for fpga
llysdal 076ea0c
Fixed error regarding execution count sometimes not being set
llysdal 9a85c1e
Removed some unnecessary comments
llysdal 49e8ada
Remove more unnecessary comments
llysdal 6752432
Moved fpgachip default file to wire default data generator
llysdal eec3667
Moved fpga help html
llysdal 011c771
Moved fpga help html to data_static
llysdal 298a07f
Update data version
Astralcircle 471e4e0
Merge branch 'wire-fpga' of https://github.com/llysdal/wire into wire…
Astralcircle 16430fc
Revert my commit
Astralcircle d09da0d
Merge branch 'wire-fpga' of https://github.com/llysdal/wire into wire…
Astralcircle 5700736
Recreate the folder every time it is deleted (fix from e2 editor)
Astralcircle 728e84d
Add check if client didn't downloaded content for some reason
Astralcircle c34d4e5
Don't need AddCSLuaFile on client
Astralcircle File filter
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1 @@ | ||
| --~'ExecutionInterval":n0.1;'Position":{n1.1418162550195;12.569567826814}'ExecuteOn":{~'Timed":b1'Trigger":b0'Inputs":b1}'Name":'Hello World!"'Nodes":{{~'ioName":'A"'gate":'normal-input"'connections":{}'type":'fpga"'y":n-20;'x":n-45}{~'ioName":'B"'gate":'normal-input"'connections":{}'type":'fpga"'y":n-5;'x":n-45}{~'gate":'+"'connections":{{n1;1}{n2;1}}'type":'wire"'y":n-20;'x":n-5}{~'ioName":'Add"'gate":'normal-output"'connections":{{n3;1}}'type":'fpga"'y":n-20;'x":n35}{~'ioName":'RotatedBy"'gate":'angle-input"'connections":{}'type":'fpga"'y":n40;'x":n-45}{~'ioName":'Vector"'gate":'vector-input"'connections":{}'type":'fpga"'y":n25;'x":n-45}{~'gate":'vector_rotate"'connections":{{n6;1}{n5;1}}'type":'wire"'y":n30;'x":n-5}{~'ioName":'Rotated"'gate":'string-output"'connections":{{n9;1}}'type":'fpga"'y":n30;'x":n35}{~'gate":'vector_tostr"'connections":{{n7;1}}'type":'wire"'y":n30;'x":n15}{~'ioName":'Text"'gate":'string-output"'connections":{{n11;1}}'type":'fpga"'y":n55;'x":n35}{~'gate":'string-constant"'connections":{}'value":'Hello World!"'type":'fpga"'y":n55;'x":n-5}{~'x":n20;'connections":{}'value":'Hello world!"'type":'editor"'y":n0;'visual":'label"}@{~'x":n20;'connections":{}'value":'Here's a comment"'type":'editor"'visual":'comment"'y":n5}}'Zoom":n6.6919658530683; |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,189 @@ | ||
| FPGAHelperHTML = [[ | ||
| <!DOCTYPE html> | ||
| <html> | ||
| <head> | ||
| <style> | ||
| body {background-color: white; margin-right: 30px;} | ||
| h1 {font-family: Verdana, sans-serif;} | ||
| h2, h3, h4 {margin-bottom: 0; font-family: Verdana, sans-serif;} | ||
| p {margin-top: 0; font-family: Verdana, sans-serif;} | ||
| th, td {font-family: Verdana, sans-serif;} | ||
| </style> | ||
| </head> | ||
| <body> | ||
| <h1>FPGA Help</h1> | ||
|
|
||
| <h2>Types</h2> | ||
| <div class="col" style="margin-left: 20px;"> | ||
| <table> | ||
| <tr> | ||
| <th style="width: 60px;">Type</th> | ||
| <th style="width: 80px;">Color</th> | ||
| </tr> | ||
| <tr> | ||
| <td>Normal</td> | ||
| <td style="background-color: rgb(190, 190, 255)"></td> | ||
| </tr> | ||
| <tr> | ||
| <td>Vector</td> | ||
| <td style="background-color: rgb(70, 160, 255)"></td> | ||
| </tr> | ||
| <tr> | ||
| <td>Angle</td> | ||
| <td style="background-color: rgb(100, 200, 100)"></td> | ||
| </tr> | ||
| <tr> | ||
| <td>String</td> | ||
| <td style="background-color: rgb(250, 160, 90)"></td> | ||
| </tr> | ||
| <tr> | ||
| <td>Array</td> | ||
| <td style="background-color: rgb(20, 110, 20)"></td> | ||
| </tr> | ||
| <tr> | ||
| <td>Entity</td> | ||
| <td style="background-color: rgb(255, 100, 100)"></td> | ||
| </tr> | ||
| <tr> | ||
| <td>Ranger</td> | ||
| <td style="background-color: rgb(130, 100, 60)"></td> | ||
| </tr> | ||
| <tr> | ||
| <td>Wirelink</td> | ||
| <td style="background-color: rgb(200, 80, 200)"></td> | ||
| </tr> | ||
| </table> | ||
| </div> | ||
|
|
||
| <h2>Controls</h2> | ||
| <div class="col" style="margin-left: 20px;"> | ||
| <table> | ||
| <tr> | ||
| <th style="width: 180px;">Key</th> | ||
| <th>Effect</th> | ||
| </tr> | ||
| <tr> | ||
| <td>Left mouse button</td> | ||
| <td>Used to move gates, draw connections, and draw selections</td> | ||
| </tr> | ||
| <tr> | ||
| <td>Double click</td> | ||
| <td>Draw connection from all the gates inputs / outputs</td> | ||
| </tr> | ||
| <tr> | ||
| <td>Right mouse button</td> | ||
| <td>Hold and drag mouse around to move around the internals of the FPGA</td> | ||
| </tr> | ||
| <tr> | ||
| <td>C</td> | ||
| <td>Creates a gate at the cursor position. Select which gate in the gate selector on the right</td> | ||
| </tr> | ||
| <tr> | ||
| <td>X</td> | ||
| <td>Removes the gate under the cursor. If a selection has been made, it will delete all selected gates</td> | ||
| </tr> | ||
| <tr> | ||
| <td>E</td> | ||
| <td>Edits a property of the gate under the cursor. Applicable for Input, Output and Constant gates</td> | ||
| </tr> | ||
| <tr> | ||
| <td>G</td> | ||
| <td>Toggles align to grid</td> | ||
| </tr> | ||
| <tr> | ||
| <td>Ctrl C</td> | ||
| <td>Copies the selected gates</td> | ||
| </tr> | ||
| <tr> | ||
| <td>Ctrl V</td> | ||
| <td>Pastes the previously copied gates, and marks the pasted gates as selected</td> | ||
| </tr> | ||
| </table> | ||
| </div> | ||
|
|
||
| <h2>Execution</h2> | ||
| <div class="col" style="margin-left: 20px;"> | ||
| <p>The FPGA can be made to execute on different conditions. | ||
| As default, it will execute if one of the inputs changes, or if it has a <i>timed</i> gate (as marked by red) inside it. | ||
| It should be noted that if 2 different inputs change the same tick, the FPGA will execute twice, | ||
| where the first execution will be with an old value for one of the inputs. This is due to how Wiremod works, where only one input is triggered at a time. | ||
| </p> | ||
| <p> | ||
| To further customize chip execution, there are 3 different ways a chip can trigger an execution. | ||
| </p> | ||
| <h4>Inputs</h4> | ||
| <div class="col" style="margin-left: 20px;"> | ||
| <p> | ||
| The chip executes when an input is changed, and propagates the changes inside it, updating the gates affected by the input change. | ||
| Gates that aren't affected by the input change, will not execute. | ||
| </p> | ||
| </div> | ||
| <h4>Timed</h4> | ||
| <div class="col" style="margin-left: 20px;"> | ||
| <p> | ||
| Timed execution only affects gates which are timed (marked by red). | ||
| This includes gates such as 'OS Time' and 'Entity Position', which share the property that their output is time dependant. | ||
| For these gates to always have the correct output, timed execution needs to be on. | ||
| The frequency that these timed gates are updated with can be controlled with the <b>Execution Interval</b> setting. | ||
| </p> | ||
| </div> | ||
| <h4>Trigger In</h4> | ||
| <div class="col" style="margin-left: 20px;"> | ||
| <p> | ||
| For the greatest control over executions, the other options can be turned off and this one turned on. | ||
| The gate will get a "Trigger" input, which when set to something other than 0, will cause the chip to execute everything necessary. | ||
| The FPGA keeps a "lazy queue", such that it knows which gates will need to execute when the "Trigger" input is triggered. | ||
| This includes all timed gates, and input gates which have had their value changed since last trigger. | ||
| </p> | ||
| </div> | ||
| <br> | ||
| <h3>Special execution gates</h3> | ||
| <div class="col" style="margin-left: 20px;"> | ||
| <p> | ||
| To further customize how a chip executes, some special execution gates have been included. | ||
| They can be found under FPGA/Execution | ||
| <h4>Execution Delta</h4> | ||
| <div class="col" style="margin-left: 20px;"> | ||
| <p> | ||
| This chip will return the time between the current execution and the last one. | ||
| Useful for time critical circuitry - such as levitating - or calculations where the time difference is required. | ||
| </p> | ||
| </div> | ||
| <h4>Execution Count</h4> | ||
| <div class="col" style="margin-left: 20px;"> | ||
| <p> | ||
| Increments by one each time the chip executes | ||
| </p> | ||
| </div> | ||
| <h4>Last (Normal/Vector/Angle/String)</h4> | ||
| <div class="col" style="margin-left: 20px;"> | ||
| <p> | ||
| Mainly designed to allow looping circuitry. For example, a memory gate feeding it's own value + 1 into itself will produce an infinite loop. | ||
| If a Last gate is put somewhere in the loop, it will allow it to be executed. It does this by using the value the gate connected to it's input had last execution, | ||
| 'disengaging' the infinite loop. | ||
| </p> | ||
| </div> | ||
| <h4>Previous (Normal/Vector/Angle/String)</h4> | ||
| <div class="col" style="margin-left: 20px;"> | ||
| <p> | ||
| An alternative to the Last gate, that functions a bit differently. This gate will output the value the connected gate had the previous tick, | ||
| which differs from the Last gate behaviour both because multiple executions can happen each tick, which will cause the Last gate to change, but not the Previous gate. | ||
| The most important difference, is that the Previous gate will trigger a new execution during next tick, with the updated value. | ||
| This can cause a chain reaction, if this execution changes the Previous gate, causing it to trigger next tick again. | ||
| To avoid such chain reactions, the value should somehow stabilize - but the internal circuitry decides that. | ||
| </p> | ||
| </div> | ||
| <h4>Last Timed (Normal/Vector/Angle/String)</h4> | ||
| <div class="col" style="margin-left: 20px;"> | ||
| <p> | ||
| Alternative form of the Last gate, this one can trigger an execute if the FPGA is set to trigger on Timed. | ||
| This is useful for loops that are meant to execute every Execution Interval, where you don't care if the value has actually changed or not. | ||
| </p> | ||
| </div> | ||
| </p> | ||
| </div> | ||
| </div> | ||
|
|
||
| </body> | ||
| </html> | ||
| ]] |
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