Add Verification and Regression Tests for base/ and axi/#1386
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Add Verification and Regression Tests for base/ and axi/#1386bengineerd wants to merge 62 commits intopre-releasefrom
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- Introduced three new markdown files outlining the objectives, methodologies, and progress for the SURF RTL regression system. - The documents detail the transition to a Python-only executable test framework, the scope of the regression efforts, and the planned phases for implementation. - Included immediate next tasks and important repo facts to guide future development and ensure consistency across the regression process.
- Added the initial regression inventory schema in `docs/_meta/rtl_regression_inventory.yaml`, detailing the first pilot modules: `FifoAsync`, `AxiStreamFifoV2`, and `AxiLiteAsync`. - Updated the handoff documentation to reflect the inclusion of the inventory and the selected pilot modules. - Defined the next steps for implementing the shared Python regression helper structure and initiating the first pilot regression.
- Introduced `scripts/setup_regression_env.sh` to automate the local environment setup for the regression framework, including virtual environment creation and dependency installation. - Added `.vscode/tasks.json` to define tasks for setting up the regression environment, importing HDL sources, and running regression tests. - Updated documentation to reflect the new bootstrap process and local `ruckus` linking, ensuring a smoother workflow for future development.
…itial pilot implementation - Established a structured layout for regression tests under `tests/`, categorizing them by subsystem to improve organization and maintainability. - Implemented the first pilot regression for `FifoAsync`, validating its functionality with a comprehensive test suite located in `tests/base/fifo/test_FifoAsync.py`. - Introduced shared regression helpers in `tests/common/regression_utils.py` to streamline future test implementations. - Updated the regression inventory to reflect the new test paths and statuses, ensuring clarity on the progress of pilot modules. - Documented the new test layout policy in `tests/README.md` to guide future contributions and maintain consistency across the regression framework.
…tation enhancements - Documented the results of a quick HDL coverage check against the local Homebrew `ghdl` build, noting the absence of `--coverage` support. - Highlighted the need for a separate tooling decision regarding HDL source coverage availability with the current `ghdl` LLVM build. - Added insights on the effectiveness of existing Python regressions as reusable verification assets and emphasized the importance of maintaining a structured test layout.
…entation updates - Migrated `AxiStreamFifoV2` regression tests into a structured package under `tests/axi/axi_stream/`, implementing a new test file that follows the shared helper structure. - Added a purpose-built thin wrapper for `AxiLiteAsync` and initiated its regression tests under `tests/axi/axi_lite/`. - Updated the regression inventory to reflect the new test paths and statuses, ensuring clarity on the progress of pilot modules. - Enhanced documentation to emphasize the importance of commenting new Python regression code for better understanding of test intent and framework behavior. - Organized new regressions by subsystem to improve maintainability and clarity in the test structure.
- Introduced a new `pytest.ini` file to set default options for parallel test execution using xdist. - Updated the CI workflow to align with the new pytest configuration, removing redundant command-line options. - Expanded the `FifoAsync` regression test suite to include a validated 12-case parameter matrix, improving coverage and organization. - Enhanced documentation to reflect the new pytest defaults and the structure of the expanded regression tests.
- Added a new section to the RTL regression plan outlining the coverage policy for VHDL packages, specifying that they are treated transitively unless a behavioral function requires a dedicated wrapper. - Updated the RTL regression handoff and progress documents to reflect the new policy, ensuring clarity on the treatment of VHDL packages in the regression framework.
…tantiation graph
- Implemented and validated an 11-case regression matrix for `FifoSync`, adding the test suite in `tests/base/fifo/test_FifoSync.py`.
- Introduced a first-pass RTL instantiation graph, generated and checked in as `docs/_meta/rtl_instantiation_graph.{md,json}`, to guide bottom-up rollout decisions.
- Updated documentation to reflect the new test structure and the instantiation graph's role in planning future regression efforts.
- Introduced a new RTL instantiation graph in `docs/_meta/rtl_instantiation_graph.{md,json}` to assist in bottom-up rollout decisions and reduce redundant testing across hierarchy levels.
- The graph summarizes entity and edge counts, highlights duplicate entity names, and provides insights into instantiated entities and assemblers.
- Updated related documentation to reflect the graph's role in guiding future regression efforts and planning strategies.
- Added a new regression test suite for the `Synchronizer` module, including a validated 6-case parameter matrix in `tests/base/sync/test_Synchronizer.py`. - Updated the RTL regression handoff and inventory documentation to reflect the addition of the `Synchronizer` and its test coverage. - Enhanced guidance on using the repo's virtual environment for local Python commands to ensure consistent execution across different setups.
…documentation updates - Added regression tests for `SynchronizerVector`, `RstPipeline`, `SimpleDualPortRam`, `FifoOutputPipeline`, and `FifoWrFsm`, each with validated parameter matrices in their respective test files. - Updated the RTL regression handoff and inventory documentation to reflect the new modules and their coverage. - Enhanced guidance on commenting new Python regression code to adopt a tutorial-style approach, ensuring clarity for readers unfamiliar with cocotb. - Organized new regressions under subsystem packages to improve maintainability and clarity in the test structure.
…ve test coverage - Implemented and validated regression tests for `Crc32Parallel`, `Crc32`, and `CRC32Rtl`, each with detailed parameter matrices in their respective test files. - Added a new test utility module for CRC operations to streamline test implementations and maintain consistency. - Updated the RTL regression handoff and inventory documentation to reflect the addition of new modules and their validated coverage. - Enhanced the existing regression framework by organizing tests under subsystem packages and improving the structure of shared helper functions. - Documented the use of a thin wrapper for `Crc32` to address simulator limitations with generic overrides, ensuring clarity for future implementations.
…ng coverage and organization - Added regression tests for `Arbiter`, `ClockDivider`, `Debouncer`, `Gearbox`, `Heartbeat`, `Mux`, `OneShot`, `RegisterVector`, `RstPipelineVector`, `Scrambler`, `WatchDogRst`, `SlvDelay`, and `SlvFixedDelay`, each with validated parameter matrices in their respective test files. - Introduced a shared generated-wrapper path in `tests/common/regression_utils.py` and migrated `Heartbeat` and `Debouncer` tests away from checked-in one-off VHDL wrappers to streamline future implementations. - Updated the RTL regression handoff and progress documentation to reflect the expanded coverage and the new test organization structure. - Enhanced guidance on using generated wrappers for real- or vector-generic leaves to maintain clarity and reduce clutter in the repository.
- Added detailed comments throughout the `SlvDelay`, `SlvFixedDelay`, and various general test files to improve understanding of test behavior and expectations. - Updated testbench initialization to ensure clocks are started early, allowing tests to focus on stimulus and output verification. - Enhanced reset behavior tests to confirm state changes and proper handling of edge cases, ensuring robust validation of module functionality.
…verage and organization - Added regression tests for `DspComparator`, `Fifo`, `FifoCascade`, `FifoMux`, and `AsyncGearbox`, each with validated parameter matrices in their respective test files. - Introduced a shared generated-wrapper path in `tests/common/regression_utils.py` and migrated relevant tests to streamline future implementations. - Updated the RTL regression handoff and progress documentation to reflect the expanded coverage and new test organization structure. - Enhanced guidance on using generated wrappers for real- or vector-generic leaves to maintain clarity and reduce clutter in the repository.
…ests - Completed the implementation and validation of the remaining non-vendor, non-dummy `base/` modules: `MasterRamIpIntegrator`, `SlaveRamIpIntegrator`, `DualPortRam`, `SlvDelayRam`, `SlvDelayFifo`, `SyncClockFreq`, `SyncTrigRate`, and `SyncTrigRateVector`. - Added corresponding regression tests for each module, ensuring comprehensive coverage and functionality. - Updated the RTL regression handoff and inventory documentation to reflect the newly validated modules and their test statuses. - Enhanced the regression progress documentation to indicate the completion of the practical phase-1 rollout for the `base/` modules, with only `LutFixedDelay` remaining deferred due to vendor dependencies.
- Introduced a new utility module `ram_test_utils.py` to facilitate dual-clock RAM testing, including methods for clock management and reset handling. - Refactored existing dual-port RAM tests to utilize the new utility, improving code organization and reducing redundancy. - Enhanced test methodologies for `DualPortRam`, `SimpleDualPortRam`, and `TrueDualPortRam` to cover various operational modes and reset behaviors. - Updated documentation to reflect the new test structure and methodologies, ensuring clarity and maintainability in the regression framework.
…idelines - Updated the documentation for Python regression tests to require a two-layer comment style: a module-specific `Test methodology` block and in-body tutorial comments. - The methodology block must include wrapped bullets for `Sweep`, `Stimulus`, `Checks`, and `Timing`, detailing the specific behavior of the module under test. - Emphasized the importance of clarity and readability in comments to assist users unfamiliar with cocotb, ensuring that both the methodology and tutorial comments serve distinct purposes.
- Introduced the `AxiStreamPipelineIpIntegrator.vhd` as a thin flat-port wrapper for the `AxiStreamPipeline`, enabling streamlined integration with cocotb. - Implemented regression tests for `AxiStreamPipeline` in `tests/axi/axi_stream/test_AxiStreamPipeline.py`, covering zero-stage pass-through, staged pipeline behavior, and reset handling. - Added validation tests for `AxiLiteCrossbar` in `tests/axi/axi_lite/test_AxiLiteCrossbar.py`, focusing on address decoding, transaction routing, and concurrent traffic management. - Updated documentation to reflect the new modules and their testing methodologies, ensuring clarity and maintainability in the regression framework.
- Updated the RTL regression handoff to clarify that the reviewed flat module build order in `rtl_regression_plan.md` is now the primary source for implementation tasks, replacing the need to re-analyze the instantiation graph for daily operations. - Documented the current phase-1 build order, detailing completed modules and the next queued items, ensuring a streamlined approach for future development. - Emphasized the importance of using the flat build order for day-to-day target selection while retaining the instantiation graph for provenance and justified reordering decisions.
- Introduced the `AxiStreamMuxIpIntegrator.vhd` as a thin flat-port wrapper for the `AxiStreamMux`, facilitating integration with cocotb. - Implemented regression tests in `tests/axi/axi_stream/test_AxiStreamMux.py`, covering indexed arbitration with explicit priority, routed `TDEST`/`TID` remap under backpressure, and staged asynchronous reset behavior. - Updated documentation to reflect the new module and its testing methodologies, ensuring clarity and maintainability in the regression framework. - Validated the `AxiStreamMux` functionality, confirming proper handling of `disableSel` and priority masking in the test scenarios.
- Introduced the `AxiStreamDeMuxIpIntegrator.vhd` as a thin flat-port wrapper for the `AxiStreamDeMux`, enabling integration with cocotb. - Implemented regression tests in `tests/axi/axi_stream/test_AxiStreamDeMux.py`, covering indexed routing to both outputs, routed exact-match decode under output backpressure, and dynamic-route table behavior including unmatched-destination drop and staged asynchronous reset flush. - Updated documentation to reflect the new module and its testing methodologies, ensuring clarity and maintainability in the regression framework. - Validated the `AxiStreamDeMux` functionality, confirming proper handling of routing and reset behaviors in the test scenarios.
- Introduced `AxiLiteAsyncIpIntegrator.vhd`, `AxiLiteMasterIpIntegrator.vhd`, `AxiStreamResizeIpIntegrator.vhd`, and `AxiLiteToDrpIpIntegrator.vhd` as thin flat-port wrappers for their respective modules, enabling integration with cocotb. - Implemented regression tests for each new module in their respective test files, ensuring comprehensive coverage of functionality, including request/ack sequencing, reset behaviors, and data handling. - Updated documentation to reflect the new modules and their testing methodologies, ensuring clarity and maintainability in the regression framework. - Validated the functionality of the new modules, confirming proper operation in various test scenarios, including common-clock and asynchronous reset conditions.
- Updated the RTL instantiation graph in `rtl_instantiation_graph.json` and `rtl_instantiation_graph.md` to reflect changes in entity and edge counts, now totaling 686 entities and 1336 edges. - Added new entries for `AxiLiteMaster`, `AxiStreamMux`, and `AxiStreamDeMux` with updated instantiation counts. - Introduced a new phase-1 queue in `rtl_phase1_queue.json` and `rtl_phase1_queue.md`, detailing the bottom-up order of modules for implementation, with manual deferrals and overrides documented in `rtl_phase1_queue_overrides.json`. - Enhanced documentation to clarify the new workflow for module implementation, emphasizing the use of the generated phase-1 queue as the primary source of truth for development tasks.
- Introduced `AxiReadPathMuxIpIntegrator.vhd`, `AxiWritePathMuxIpIntegrator.vhd`, `AxiResizeIpIntegrator.vhd`, and `AxiToAxiLiteIpIntegrator.vhd` as new modules for AXI4 integration, enabling streamlined functionality with cocotb. - Implemented regression tests for each new module in their respective test files, ensuring comprehensive coverage of functionality, including read/write operations and data handling. - Updated documentation to reflect the new modules and their testing methodologies, ensuring clarity and maintainability in the regression framework. - Validated the functionality of the new modules, confirming proper operation in various test scenarios, including concurrent access and data integrity checks.
- Introduced multiple new modules including `AxiLiteMasterProxyIpIntegrator.vhd`, `AxiLiteSequencerRamIpIntegrator.vhd`, `AxiStreamCompactIpIntegrator.vhd`, `AxiStreamConcatIpIntegrator.vhd`, `AxiStreamFrameRateLimiterIpIntegrator.vhd`, `AxiStreamPrbsFlowCtrlIpIntegrator.vhd`, `AxiStreamRepeaterIpIntegrator.vhd`, and `AxiStreamShiftIpIntegrator.vhd` to enhance AXI integration capabilities. - Implemented regression tests for each new module, ensuring comprehensive coverage of functionality, including data handling and reset behaviors. - Updated documentation to reflect the new modules and their testing methodologies, ensuring clarity and maintainability in the regression framework. - Validated the functionality of the new modules, confirming proper operation in various test scenarios, including concurrent access and data integrity checks.
- Introduced multiple new modules including `AxiStreamTapIpIntegrator.vhd`, `AxiStreamTimerIpIntegrator.vhd`, `AxiStreamTrailerRemoveIpIntegrator.vhd`, `AxiLiteToIpBusIpIntegrator.vhd`, and `IpBusToAxiLiteIpIntegrator.vhd` to enhance AXI integration capabilities. - Implemented regression tests for each new module, ensuring comprehensive coverage of functionality, including data handling and reset behaviors. - Updated documentation to reflect the new modules and their testing methodologies, ensuring clarity and maintainability in the regression framework. - Validated the functionality of the new modules, confirming proper operation in various test scenarios, including concurrent access and data integrity checks.
- Added entries to .gitignore for local editor and agent state files, including .vscode/ and .cursor/. - Removed the .vscode/tasks.json file as it is no longer needed, streamlining the project structure.
- Added concurrency settings to the CI workflow to manage simultaneous runs and cancel in-progress jobs. - Removed unnecessary fetch-depth configuration from checkout steps to streamline the workflow.
- Standardized the formatting of port declarations across multiple AXI Stream and AXI Lite IP Integrator files, ensuring uniformity in code style. - Updated `AxiStreamCombinerIpIntegrator.vhd`, `AxiStreamDeMuxIpIntegrator.vhd`, `AxiStreamFifoV2IpIntegrator.vhd`, `AxiStreamPipelineIpIntegrator.vhd`, `AxiStreamResizeIpIntegrator.vhd`, and `AxiLiteToDrpIpIntegrator.vhd` to improve readability and maintainability.
- Modified the CI workflow to rename the VHDL regression testing step to "Parallel Regression Tests" and adjusted the pytest command to include specific test directories with concurrency options. - Removed the `addopts` setting from `pytest.ini` to streamline test execution, maintaining the `norecursedirs` configuration for legacy tests.
- Standardized the formatting of port declarations across multiple AXI Lite and AXI Stream IP Integrator files, enhancing code readability and maintainability. - Updated files including `AxiLiteAsyncIpIntegrator.vhd`, `AxiLiteMasterIpIntegrator.vhd`, `AxiLiteMasterProxyIpIntegrator.vhd`, `AxiLiteSequencerRamIpIntegrator.vhd`, `AxiLiteSlaveIpIntegrator.vhd`, `AxiLiteWriteFilterIpIntegrator.vhd`, and various AxiStream modules to ensure uniformity in style.
- Introduced the `AxiRateGenIpIntegrator.vhd` file, implementing a new AXI Rate Generator IP Integrator with configurable parameters for address, data, and ID widths. - Added a corresponding test file `test_AxiRateGen.py` to validate the functionality of the AxiRateGen module, ensuring proper operation of AXI-Lite register programming and generated AXI traffic. - Updated documentation to reflect the addition of the AxiRateGen module and its testing methodology, maintaining clarity and consistency in the regression framework.
- Introduced `AxiLiteFifoPopIpIntegrator.vhd`, `AxiLiteFifoPushIpIntegrator.vhd`, `AxiLiteFifoPushPopIpIntegrator.vhd`, `AxiLiteRingBufferIpIntegrator.vhd`, `AxiStreamScatterGatherIpIntegrator.vhd`, `AxiMemTesterIpIntegrator.vhd`, and `AxiReadPathFifoIpIntegrator.vhd` files, implementing wrappers for various AXI components. - Each integrator facilitates specific functionalities such as FIFO operations and memory testing, enhancing the AXI framework. - Updated documentation to reflect the new components and their intended use cases, ensuring clarity for future development and integration efforts.
- Introduced `AxiStreamBatchingFifoIpIntegrator.vhd`, `AxiStreamMonIpIntegrator.vhd`, `AxiStreamRingBufferIpIntegrator.vhd`, and `AxiStreamDmaV2IpIntegrator.vhd` files, implementing wrappers for various AXI Stream and DMA components. - Each integrator enhances the AXI framework by providing specific functionalities such as batching, monitoring, and ring buffering of AXI streams, as well as DMA operations. - Updated the regression tests to validate the functionality of the new components, ensuring proper integration and performance within the AXI ecosystem. - Revised documentation to reflect the new components and their intended use cases, maintaining clarity for future development and integration efforts.
- Modified `test_AxiResize.py` to mark the "upsize" parameter case as expected to fail due to a known RTL bug related to resizing from 32-bit to 64-bit. - Updated `test_AxiStreamDmaV2Read.py` to mark the "single_frame_read" test case as expected to fail due to a known RTL bug causing simulation aborts. - These changes ensure that the test suite accurately reflects the current limitations of the RTL implementation while maintaining test coverage.
- Modified the `setup_regression_env.sh` script to include parallel test execution with the `-n auto --dist=worksteal` options for specific test directories. - Added a command to run all test files matching the pattern `tests/test_*.py`, improving the flexibility and efficiency of the regression testing process.
- Introduced multiple new files including `AxiLiteRamSyncStatusVectorIpIntegrator.vhd`, `AxiStreamMonAxiLIpIntegrator.vhd`, `AxiMonAxiLIpIntegrator.vhd`, `AxiReadEmulateIpIntegrator.vhd`, `AxiRingBufferIpIntegrator.vhd`, `AxiWriteEmulateIpIntegrator.vhd`, `AxiStreamDmaFifoIpIntegrator.vhd`, and `AxiStreamDmaIpIntegrator.vhd`, implementing wrappers for different AXI components. - Each integrator enhances the AXI framework by providing specific functionalities such as RAM synchronization, stream monitoring, read emulation, ring buffering, and DMA operations. - Updated documentation to reflect the new components and their intended use cases, ensuring clarity for future development and integration efforts.
- Introduced `utils.py` to centralize AXI-related utility functions, including `axil_read_u32`, `axil_write_u32`, and `ring_buffer_axil_addr`, improving code reusability and readability. - Refactored multiple test cases across various AXI test files to utilize the new utility functions for reading and writing AXI registers, enhancing maintainability and reducing code duplication. - Updated test method names for clarity, ensuring they accurately reflect their functionality.
- Removed the unused `AxiMaster` import from `test_AxiRateGen.py`, streamlining the code and improving readability.
- Deleted `test_AxiRingBufferTb.py` and `test_AxiStreamBatchingFifoTb.py` as they are no longer needed, streamlining the test suite. - Updated imports in other test files to utilize `cocotb_module_name_from_test_file` for improved module name handling.
- Standardized the formatting of port declarations across multiple AXI IP Integrator files, including `AxiMemTesterIpIntegrator.vhd`, `AxiRateGenIpIntegrator.vhd`, `AxiReadEmulateIpIntegrator.vhd`, `AxiWriteEmulateIpIntegrator.vhd`, and `AxiWritePathFifoIpIntegrator.vhd`. - Improved code readability by aligning signal declarations and ensuring consistent spacing, enhancing maintainability of the codebase.
- Introduced new VHDL wrapper files: `DebouncerWrapper.vhd`, `HeartbeatWrapper.vhd`, `SyncClockFreqWrapper.vhd`, `SynchronizerOneShotCntVectorFlatWrapper.vhd`, `SyncStatusVectorFlatWrapper.vhd`, `SyncTrigRateVectorFlatWrapper.vhd`, and `SyncTrigRateWrapper.vhd`. - Each wrapper provides a cocotb-facing interface for the corresponding SURF components, allowing for integer-based parameterization and improved testability. - Updated test files to utilize the new wrappers, streamlining the testing process and enhancing maintainability of the test suite. - Removed obsolete wrapper generation functions from test files to simplify the codebase and improve clarity.
- Added new signals for AXI write and read operations in `AxiMemTesterIpIntegrator.vhd`, improving the interface for AXI transactions. - Updated the `M_AXI_AWREGION` signal type in `AxiRateGenIpIntegrator.vhd` to ensure consistency in signal definitions across the integrators, enhancing code clarity and maintainability.
- Standardized spacing in port declarations across `AxiRateGenIpIntegrator.vhd`, `AxiReadEmulateIpIntegrator.vhd`, `DebouncerWrapper.vhd`, `HeartbeatWrapper.vhd`, `SyncClockFreqWrapper.vhd`, `SyncStatusVectorFlatWrapper.vhd`, and `SyncTrigRateWrapper.vhd`. - Enhanced code readability and maintainability by aligning signal declarations and ensuring consistent formatting throughout the files.
- Added instructions to run the `vsg` linter with CI's configuration on any created or edited VHDL files across multiple documentation files. - Emphasized the use of `--fix` for autofixing issues before manual cleanup to ensure code quality and consistency.
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@bengineerd Reminder that you need to add the licensing code header to all .vhd and .py files that you just created
- Introduced new VHDL wrapper files: `AxiStreamPkgWrapper.vhd`, `EventFrameSequencerWrapper.vhd`, `HammingEccWrapper.vhd`, `LineCode8b10bWrapper.vhd`, `LineCode10b12bWrapper.vhd`, `LineCode12b14bWrapper.vhd`, `Pgp4CoreLiteWrapper.vhd`, `Pgp4CoreWrapper.vhd`, `SaciAxiLiteMasterWrapper.vhd`, and `Saci2ToAxiLiteWrapper.vhd`. - Each wrapper provides a cocotb-facing interface for the corresponding SURF components, allowing for improved testability and integration. - Updated CI configuration to include additional test directories, ensuring comprehensive coverage during testing. - Enhanced the testing framework by adding new test cases that utilize the newly created wrappers, streamlining the testing process and improving maintainability of the test suite.
- Introduced `FwftCntWrapper.vhd`, `SrpV3AxiWrapper.vhd`, and `SsiResizeFifoEofeWrapper.vhd` to provide cocotb-facing interfaces for FWFT FIFO count testing, SRPv3 AXI integration, and SSI resize FIFO EOFE propagation, respectively. - Added corresponding test files: `test_FwftCnt.py`, `test_SrpV3Axi.py`, and `test_SsiResizeFifoEofe.py`, implementing comprehensive test methodologies for each wrapper. - Removed obsolete test files for FWFT, SRPv3, and SSI, streamlining the test suite and enhancing maintainability. - Updated the SRP protocol test directory structure to include an `__init__.py` file for better organization.
- Deleted multiple legacy test files including `test_AxiLiteCrossbarTb.py`, `test_AxiRamTb.py`, `test_AxiRingBufferTb.py`, `test_AxiStreamBatchingFifoTb.py`, `test_AxiStreamDemuxMuxTb.py`, `test_AxiStreamDmaReadTb.py`, `test_AxiStreamGearboxTb.py`, `test_AxiStreamPipelineTb.py`, `test_AxiStreamResizeTb.py`, and `test_AxiVersionIpIntegrator.py` as they are no longer needed, streamlining the test suite. - This cleanup enhances maintainability and reduces clutter in the codebase.
…e testing process and enhance maintainability.
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Description
Add the Phase-1 SURF RTL regression baseline for the simulator-friendly
base/,axi/, and initialdsp/modules using the project’s Python-first flow (pytest + cocotb + GHDL + ruckus). This PR adds subsystem-organized cocotb regressions, checked-in IP-integrator wrappers where flat AXI/AXI-Lite/AXIS interfaces are needed, shared regression utilities, and updated planning/progress artifacts underdocs/_meta/so rollout state is recoverable without re-discovery. It also updates CI and local setup so the new regression tiers run reliably in parallel while legacy top-level benches still run in a separate serial pass.Details
This branch validates the current axi-first Phase-1 queue through the final simulator-friendly
axi/modules and expandsbase/coverage across FIFO, sync, delay, RAM, CRC, and general utility blocks, with the firstdsp/leaf now included. It also standardizes common GHDL compile flags, cocotb module discovery helpers, pytest parallel defaults, and the generated RTL queue artifacts used by the planning docs.Known expected-open items on this branch remain:
tests/axi/axi4/test_AxiResize.pyfor the restored32-bit -> 64-bitupsize casetests/axi/dma/test_AxiStreamDmaV2Read.pydue to the current internalCONV_INTEGERassertion under GHDL