loader: set exception handler for RISC-V

[Ivan-Velickovic]

Closes #480.

[midnightveil]

Why do we bother doing this when everything else assumes 64-bit?

[Ivan-Velickovic]

I just did it since it's trivial

[midnightveil]

"rK" here means A 5-bit unsigned immediate for CSR access instructions.. Was there a reason why rK was used?

Also, don't these need a : "memory" barrier otherwise the compile is free to reorder them?

[midnightveil]

Answer: "rK" means register or 5-bit immediate; binutils in opcodes/riscv-opc.c defines:

{"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
{"csrw",       0, INSN_CLASS_ZICSR, "E,Z",   MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS },

so it is clever enough to encode a csrw in either the csrrw (register) variant or the csrrwi (immediate) variants based on which kind the %0 fits in.

	    case 'Z': /* CSRRxI immediate.  */
	      my_getExpression (imm_expr, asarg, force_reloc);
	      check_absolute_expr (ip, imm_expr, false);
	      if ((unsigned long) imm_expr->X_add_number > 31)
		as_bad (_("improper CSRxI immediate (%"PRIu64")"),
			imm_expr->X_add_number);
	      INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
	      imm_expr->X_op = O_absent;
	      asarg = expr_parse_end;
	      continue;

So this is GCC magically handling immediates as an optimisation.