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Fix bus error or segfault from roi_align with large batchsize #9441

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8c71ea8
fix the issue 8206 and add the test
Mar 13, 2026
40b2276
fix the issue 8206 and add the test
Mar 13, 2026
d9ab5ce
remove unnecessary comments
Mar 13, 2026
544d960
address the comments
Mar 17, 2026
76f6a16
add the backward kernel test
Mar 17, 2026
b6b7ab7
address the test failure
Mar 20, 2026
b0004a1
Merge branch 'main' into issue-8206
zy1git Mar 20, 2026
8ff88ed
address the comments
Mar 24, 2026
bad6aba
skip the cpu test
Mar 24, 2026
e0b1a5b
Merge branch 'main' into issue-8206
zy1git Mar 24, 2026
1d9d1d4
check the type and cast
Mar 24, 2026
f40a46d
remove the unnecessary changes and stick to the original codes
Mar 24, 2026
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37 changes: 37 additions & 0 deletions test/test_ops.py
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Original file line number Diff line number Diff line change
Expand Up @@ -643,6 +643,43 @@ def test_performance_mps(self):
execution_time_ms < execution_time_ms_threshold
), f"Expected execution to take < {execution_time_ms_threshold} ms, actually took {execution_time_ms} ms"

@pytest.mark.parametrize("device", cpu_and_cuda())
def test_roi_align_large_index(self, device):
"""Non-regression test for https://github.com/pytorch/vision/issues/8206"""
if device == "cpu":
pytest.skip("Too slow on CPU")

pooled_h, pooled_w = 7, 7
channels = 4
# 11M * 4 * 7 * 7 = 2,156,000,000 > INT_MAX
n_rois = 11_000_000
num_imgs = 2
height, width = 4, 4
spatial_scale = 1.0
sampling_ratio = 2

x = torch.rand(num_imgs, channels, height, width, dtype=torch.float32, device=device, requires_grad=True)
rois = torch.zeros(n_rois, 5, dtype=torch.float32, device=device)

rois[:, 0] = torch.randint(0, num_imgs, (n_rois,))
rois[:, 1] = 0
rois[:, 2] = 0
rois[:, 3] = width - 1
rois[:, 4] = height - 1

# Call the C++ kernel directly, in case that torchvision.ops.roi_align may fall
# back to a pure-Python path that doesn't have the int32 overflow bug.
result = torch.ops.torchvision.roi_align(x, rois, spatial_scale, pooled_h, pooled_w, sampling_ratio, False)

# Forward kernel test
assert result.shape == (n_rois, channels, pooled_h, pooled_w)
assert result.abs().sum() > 0

# Backward kernel test
result.sum().backward()
assert x.grad is not None
assert x.grad.abs().sum() > 0


class TestPSRoIAlign(RoIOpTester):
mps_backward_atol = 5e-2
Expand Down
38 changes: 20 additions & 18 deletions torchvision/csrc/ops/cpu/roi_align_kernel.cpp
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Expand Up @@ -26,7 +26,8 @@ void roi_align_forward_kernel_impl(
// can be parallelized using omp
// #pragma omp parallel for num_threads(32)
for (int n = 0; n < n_rois; n++) {
int index_n = n * channels * pooled_width * pooled_height;
int64_t index_n =
static_cast<int64_t>(n) * channels * pooled_width * pooled_height;
Comment on lines +29 to +30
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@zy1git zy1git Mar 24, 2026 •
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type and cast are good.


const T* offset_rois = rois + n * 5;
int roi_batch_ind = offset_rois[0];
Expand Down Expand Up @@ -78,14 +79,15 @@ void roi_align_forward_kernel_impl(
pre_calc);

for (int c = 0; c < channels; c++) {
int index_n_c = index_n + c * pooled_width * pooled_height;
const T* offset_input =
input + (roi_batch_ind * channels + c) * height * width;
int64_t index_n_c =
index_n + static_cast<int64_t>(c) * pooled_width * pooled_height;
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casting could be removed in the new commit.

const T* offset_input = input +
(static_cast<int64_t>(roi_batch_ind) * channels + c) * height * width;
Comment on lines +82 to +84
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type and cast are good

int pre_calc_index = 0;

for (int ph = 0; ph < pooled_height; ph++) {
for (int pw = 0; pw < pooled_width; pw++) {
int index = index_n_c + ph * pooled_width + pw;
int64_t index = index_n_c + ph * pooled_width + pw;
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type is good


T output_val = 0.;
for (int iy = 0; iy < roi_bin_grid_h; iy++) {
Expand Down Expand Up @@ -175,7 +177,7 @@ inline void add(T* address, const T& val) {

template <typename T>
void roi_align_backward_kernel_impl(
int nthreads,
int64_t nthreads,
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@NicolasHug NicolasHug Mar 16, 2026 •
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Can you explain why nthreads needs to be int64_t? It should never need to be that large? If it's for integer comparison to not warn, we could just cast?

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@zy1git zy1git Mar 17, 2026 •
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Thanks for the question. nthreads in the backward kernel is grad.numel(), which equals n_rois × channels × pooled_h × pooled_w.

I changed to int nthreads in both .cpp and .cu files and ran the test (only the forward kernel test, no backward kernel test due to the large memory requirement). The CPU test passed but the CUDA test failed with all-zero output. The reason is that the CPU forward kernel doesn't use nthreads — it loops over n_rois separately, and the overflow is handled by the int64_t changes to index_n, index_n_c, and index. The CUDA forward kernel uses a flat loop with nthreads as the bound, so truncating to int caused nthreads to wrap to a negative value, making the loop condition immediately false and skipping all output computation — resulting in all-zero output.

The CPU backward kernel does use nthreads in the same flat-loop pattern as CUDA (for (int64_t index = 0; index < nthreads; ...)) and receives the same overflowing value via grad.numel(), so it needs int64_t for the same reason.

A backward-specific test would require large memory (output + grad_output + grad_input), which might be impractical for CI. Do we want to add one with a memory skip guard, or is the current forward-only test sufficient?

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@zy1git zy1git Mar 17, 2026 •
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As for "If it's for integer comparison to not warn, we could just cast?", I think it isn't a warning issue. The problem is that the value could be actually large and gets truncated at the call site before the function body runs. In the author's reproducing example (batch_size=172, default 1000 proposals per image), nthreads is 172,000 × 256 × 7 × 7 = 2,157,568,000 > INT_MAX.

I added the backward kernel test in the latest commit. If I change int64_t nthreadsto int nthreads, the CPU backward test fails with all-zero gradients because nthreads gets truncated to a negative value and the loop never executes.

nthreads doesn't mean "number of threads" in this code, instead, it means "total number of output elements to process.", which could be very large.

Feel free to let me know if you have any questions.

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@NicolasHug NicolasHug Mar 23, 2026

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Thanks. For my own ref:

nthreads is the name for output_size in the cuda kernel:

vision/torchvision/csrc/ops/cuda/roi_align_kernel.cu

Lines 378 to 379 in d7400a3

roi_align_forward_kernel_impl<scalar_t><<<grid, block, 0, stream>>>(
output_size,

where output size was already inferred as uint64 since size() returns uint64:

vision/torchvision/csrc/ops/cuda/roi_align_kernel.cu

Lines 354 to 362 in d7400a3

auto num_rois = rois.size(0);
auto channels = input.size(1);
auto height = input.size(2);
auto width = input.size(3);
at::Tensor output = at::zeros(
{num_rois, channels, pooled_height, pooled_width}, input.options());
auto output_size = num_rois * pooled_height * pooled_width * channels;

nthreads was previously implicitly cast to int32 when passed to roi_align_forward_kernel_impl causing an overflow. Now, with the change made to the function signature, it's properly kept as int64.

const T* grad_output,
const T& spatial_scale,
int channels,
Expand All @@ -187,11 +189,11 @@ void roi_align_backward_kernel_impl(
bool aligned,
T* grad_input,
const T* rois,
int n_stride,
int c_stride,
int h_stride,
int w_stride) {
for (int index = 0; index < nthreads; index++) {
int64_t n_stride,
int64_t c_stride,
int64_t h_stride,
int64_t w_stride) {
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@zy1git zy1git Mar 24, 2026 •
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int64_t is used to be consistent with grad.stride() which returns int64_t, avoiding implicit narrowing conversions. However, the original code used int and the change is not necessary for fixing the bug, so I will use int instead of int64_t.

for (int64_t index = 0; index < nthreads; index++) {
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int64_t is needed.

// (n, c, ph, pw) is an element in the pooled output
int pw = index % pooled_width;
int ph = (index / pooled_width) % pooled_height;
Expand Down Expand Up @@ -219,10 +221,10 @@ void roi_align_backward_kernel_impl(
T bin_size_h = static_cast<T>(roi_height) / static_cast<T>(pooled_height);
T bin_size_w = static_cast<T>(roi_width) / static_cast<T>(pooled_width);

T* offset_grad_input =
grad_input + ((roi_batch_ind * channels + c) * height * width);
T* offset_grad_input = grad_input +
((static_cast<int64_t>(roi_batch_ind) * channels + c) * height * width);
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casting is needed.


int output_offset = n * n_stride + c * c_stride;
int64_t output_offset = static_cast<int64_t>(n) * n_stride + c * c_stride;
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type and cast are good.

const T* offset_grad_output = grad_output + output_offset;
const T grad_output_this_bin =
offset_grad_output[ph * h_stride + pw * w_stride];
Expand Down Expand Up @@ -359,10 +361,10 @@ at::Tensor roi_align_backward_kernel(
}

// get stride values to ensure indexing into gradients is correct.
int n_stride = grad.stride(0);
int c_stride = grad.stride(1);
int h_stride = grad.stride(2);
int w_stride = grad.stride(3);
int64_t n_stride = grad.stride(0);
int64_t c_stride = grad.stride(1);
int64_t h_stride = grad.stride(2);
int64_t w_stride = grad.stride(3);

auto rois_ = rois.contiguous();
AT_DISPATCH_FLOATING_TYPES_AND_HALF(
Expand Down
36 changes: 19 additions & 17 deletions torchvision/csrc/ops/cuda/roi_align_kernel.cu
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Expand Up @@ -67,7 +67,7 @@ __device__ T bilinear_interpolate(

template <typename T>
__global__ void roi_align_forward_kernel_impl(
int nthreads,
int64_t nthreads,
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type is good

const T* input,
const T spatial_scale,
int channels,
Expand All @@ -79,7 +79,7 @@ __global__ void roi_align_forward_kernel_impl(
bool aligned,
const T* rois,
T* output) {
CUDA_1D_KERNEL_LOOP(index, nthreads) {
CUDA_1D_KERNEL_LOOP_T(index, nthreads, int64_t) {
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type is good

// (n, c, ph, pw) is an element in the pooled output
int pw = index % pooled_width;
int ph = (index / pooled_width) % pooled_height;
Expand Down Expand Up @@ -107,8 +107,8 @@ __global__ void roi_align_forward_kernel_impl(
T bin_size_h = static_cast<T>(roi_height) / static_cast<T>(pooled_height);
T bin_size_w = static_cast<T>(roi_width) / static_cast<T>(pooled_width);

const T* offset_input =
input + (roi_batch_ind * channels + c) * height * width;
const T* offset_input = input +
(static_cast<int64_t>(roi_batch_ind) * channels + c) * height * width;
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cast is needed here.


// We use roi_bin_grid to sample the grid and mimic integral
int roi_bin_grid_h = (sampling_ratio > 0)
Expand Down Expand Up @@ -203,7 +203,7 @@ __device__ void bilinear_interpolate_gradient(

template <typename T>
__global__ void roi_align_backward_kernel_impl(
int nthreads,
int64_t nthreads,
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type is good.

const T* grad_output,
const T spatial_scale,
int channels,
Expand All @@ -215,12 +215,12 @@ __global__ void roi_align_backward_kernel_impl(
bool aligned,
T* grad_input,
const T* rois,
int n_stride,
int c_stride,
int h_stride,
int w_stride,
const int memory_span) {
CUDA_1D_KERNEL_LOOP(index, nthreads) {
int64_t n_stride,
int64_t c_stride,
int64_t h_stride,
int64_t w_stride,
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types are good.

const int64_t memory_span) {
CUDA_1D_KERNEL_LOOP_T(index, nthreads, int64_t) {
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type is good.

// (n, c, ph, pw) is an element in the pooled output
int pw = index % pooled_width;
int ph = (index / pooled_width) % pooled_height;
Expand Down Expand Up @@ -250,7 +250,8 @@ __global__ void roi_align_backward_kernel_impl(

// We need to index the gradient using the tensor strides to access the
// correct values.
const int output_offset = n * n_stride + c * c_stride;
const int64_t output_offset =
static_cast<int64_t>(n) * n_stride + c * c_stride;
Comment on lines +253 to +254
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Type is good. The cast is technically redundant since n_stride is already int64_t and the multiplication would promote automatically. I kept it to make the 64-bit intent explicit.

const T* offset_grad_output = grad_output + output_offset;
const T grad_output_this_bin =
offset_grad_output[ph * h_stride + pw * w_stride];
Expand All @@ -265,7 +266,8 @@ __global__ void roi_align_backward_kernel_impl(
// We do average (integral) pooling inside a bin
const T count = roi_bin_grid_h * roi_bin_grid_w; // e.g. = 4

const int input_offset = (roi_batch_ind * channels + c) * height * width;
const int64_t input_offset =
(static_cast<int64_t>(roi_batch_ind) * channels + c) * height * width;
Comment on lines +269 to +270
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type and cast are good.


for (int iy = 0; iy < roi_bin_grid_h; iy++) // e.g., iy = 0, 1
{
Expand Down Expand Up @@ -432,10 +434,10 @@ at::Tensor roi_align_backward_kernel(
return grad_input;
}

int n_stride = grad.stride(0);
int c_stride = grad.stride(1);
int h_stride = grad.stride(2);
int w_stride = grad.stride(3);
int64_t n_stride = grad.stride(0);
int64_t c_stride = grad.stride(1);
int64_t h_stride = grad.stride(2);
int64_t w_stride = grad.stride(3);

at::globalContext().alertNotDeterministic("roi_align_backward_kernel");

Expand Down
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