IB host-no-atomic: GDRCopy + mlx5dv Data Direct for memory-consistent low-latency signaling#753
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IB host-no-atomic: GDRCopy + mlx5dv Data Direct for memory-consistent low-latency signaling#753
host-no-atomic: GDRCopy + mlx5dv Data Direct for memory-consistent low-latency signaling#753Conversation
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/azp run mscclpp-ut |
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Azure Pipelines successfully started running 1 pipeline(s). |
Binyang2014
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Feb 27, 2026
src/core/connection.cc
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| #if defined(DEBUG_CUFLUSH) && defined(MSCCLPP_USE_CUDA) | ||
| // cuFlush path: read from imm_data then flush NIC->GPU write pipeline for visibility. | ||
| newValueHost = static_cast<uint64_t>(qp->getRecvWcImmData(i)); | ||
| MSCCLPP_CUTHROW(cuFlushGPUDirectRDMAWrites(CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TARGET_CURRENT_CTX, | ||
| CU_FLUSH_GPU_DIRECT_RDMA_WRITES_TO_OWNER)); |
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Do we need to keep this code here?
| // Direct host-side write to GPU memory via GDRCopy BAR1 mapping | ||
| remoteUpdateDstAddrMap_->copyTo(&newValueHost, sizeof(uint64_t)); | ||
| } else { | ||
| *dstPtr = newValueHost; |
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Is this valid for CUDA? Maybe we can throw error if the dstAddrMap is invalid for cuda env
src/core/connection.cc
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| #endif | ||
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| // Read dstGpuAddr from the local stored address (set by setRemoteUpdateDstAddr) | ||
| uint64_t dstGpuAddr = remoteUpdateDstAddr_; |
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A bit confused about this var. If we use host2hostSemaphore, this addr is host addr?
chhwang
changed the title
host-no-atomic mode
chhwang
changed the title
host-no-atomic: GDRCopy + mlx5dv Data Direct for memory-consistent low-latency signaling
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Fix potential memory inconsistency in IB host-no-atomic mode, and reduce latency overhead by introducing GDRCopy.