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[syn] Adapt for Yosys 0.60 #2354

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[syn] Adapt for Yosys 0.60 #2354

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12 changes: 7 additions & 5 deletions syn/python/get_kge.py
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@marnovandermaas marnovandermaas Jan 19, 2026

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Can you explain the changes in this file. Previously the code used data 0 and data 1. Now you are also using data 2 but not data 1.

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@Zxis233 Zxis233 Jan 20, 2026 •
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Can you explain the changes in this file. Previously the code used data 0 and data 1. Now you are also using data 2 but not data 1.

The area report in Yosys 0.60 contains content similar to the following:

        +----------Local Count, excluding submodules.
        |        +-Local Area, excluding submodules.
        |        | 
      372  395.808   AND2_X1
       98   130.34   AND3_X1

That is, the real cell name is the third field, while the old code assumed that the cell name is the first field

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@marnovandermaas marnovandermaas Jan 21, 2026

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Thanks for the explanation. Is that a change that was introduced in Yosys?

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@Zxis233 Zxis233 Jan 21, 2026

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Thanks for the explanation. Is that a change that was introduced in Yosys?

I've checked the commit history and I find it:
https://github.com/YosysHQ/yosys/commit/a0dde68487da600c569c0b61b684dc845fd5c554

Clearly the area report had been refactored, but it was NOT mentioned in the update log.

Original file line number Diff line number Diff line change
Expand Up @@ -49,15 +49,17 @@ def get_kge(report_path, weighted_dict):
ge = 0.0
for line_idx, line in enumerate(report):
data = line.split()
if not data:
if len(data) < 3:
continue
weight = weighted_dict.get(data[0])
cell_name = data[2]
weight = weighted_dict.get(cell_name)
if weight is not None:
try:
ge += float(data[1]) * weight
count = float(data[0])
ge += count * weight
except (IndexError, ValueError):
raise RuntimeError('{}:{} Cell {} matched but was misformatted'
.format(report_path, line_idx + 1, data[0]))
.format(report_path, line_idx + 1, cell_name))
print("Area in kGE = ", round(ge/1000, 2))


Expand All @@ -77,4 +79,4 @@ def main():


if __name__ == "__main__":
main()
main()
18 changes: 10 additions & 8 deletions syn/syn_yosys.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -40,10 +40,10 @@ LR_DEP_SOURCES=(
"../vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_39_32_dec.sv"
"../vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_39_32_enc.sv"
"../vendor/lowrisc_ip/ip/prim/rtl/prim_lfsr.sv"
"../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_and2.sv"
"../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv"
"../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_mux2.sv"
"../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop.sv"
"../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_and2.sv"
"../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_buf.sv"
"../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_clock_mux2.sv"
"../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_flop.sv"
)

mkdir -p "$LR_SYNTH_OUT_DIR/generated"
Expand Down Expand Up @@ -78,10 +78,15 @@ for file in ../rtl/*.sv; do
continue
fi

# Skip tracer (not needed for synthesis)
if [ "$module" = "ibex_tracer" ]; then
continue
fi

sv2v \
--define=SYNTHESIS --define=YOSYS \
../rtl/*_pkg.sv \
../vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv \
../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_ram_1p_pkg.sv \
../vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv \
-I../vendor/lowrisc_ip/ip/prim/rtl \
-I../vendor/lowrisc_ip/dv/sv/dv_utils \
Expand All @@ -96,9 +101,6 @@ for file in ../rtl/*.sv; do
sed -i 's/prim_flop/prim_generic_flop/g' "$LR_SYNTH_OUT_DIR"/generated/"${module}".v
done

# remove tracer (not needed for synthesis)
rm -f "$LR_SYNTH_OUT_DIR"/generated/ibex_tracer.v

# remove the FPGA & register-based register file (because we will use the
# latch-based one instead)
rm -f "$LR_SYNTH_OUT_DIR"/generated/ibex_register_file_ff.v
Expand Down