[svsim] Expose full debug visibility in VCS waves

[jackkoenig]

Contributor Checklist

• Did you add Scaladoc to every public function/method?
• Did you add at least one test demonstrating the PR?
• Did you delete any extraneous printlns/debugging code?
• Did you specify the type of improvement?
• Did you add appropriate documentation in docs/src?
• Did you request a desired merge strategy?
• Did you add text to be included in the Release Notes for this change?

Type of Improvement

• Feature (or new API)

Desired Merge Strategy

• Squash

Release Notes

Expose -debug_access+all for VCS via new TraceSettings.fullDebugVisibility

Reviewer Checklist (only modified by reviewer)

• Did you add the appropriate labels? (Select the most appropriate one based on the "Type of Improvement")
• Did you mark the proper milestone (Bug fix: 3.6.x, 5.x, or 6.x depending on impact, API modification or big change: 7.0)?
• Did you review?
• Did you check whether all relevant Contributor checkboxes have been checked?
• Did you do one of the following when ready to merge:
  • Squash: You/ the contributor Enable auto-merge (squash) and clean up the commit message.
  • Merge: Ensure that contributor has cleaned up their commit history, then merge with Create a merge commit.

[seldridge]

There's a hidden requirement that fullDebugVisibility should not be true if both enableVcd and enableVpd are false. Maybe add a require check for this?

[seldridge]

I tend towards making these directly mirror the available VCS options nearly exactly. A better approach may be to do something like how coverage works. See: https://github.com/chipsalliance/chisel/blob/main/svsim/src/main/scala/vcs/Backend.scala#L136

I can give you a table with all the options if you want to go ham with this and just add everything once and we can be done with it forever.

[jackkoenig]

Closing in favor of #5234