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Add DynamicGroup for runtime-defined option groups #5229
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
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@@ -30,6 +30,41 @@ package object choice { | |
| final implicit def group: Group = this | ||
| } | ||
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| /** Dynamic option group that accepts a name and case names as runtime parameters. | ||
| * @example {{{ val platform = new DynamicGroup("Platform", Seq("FPGA", "ASIC")) }}} | ||
| */ | ||
| class DynamicGroup(val groupName: String, caseNames: Seq[String])(implicit _sourceInfo: SourceInfo) { | ||
| import chisel3.internal.Builder | ||
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| private[chisel3] def sourceInfo: SourceInfo = _sourceInfo | ||
| private[chisel3] def name: String = groupName | ||
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| private val _group: Group = Builder.getOrCreateDynamicGroup(groupName, caseNames, () => { | ||
| object DynamicGroupSingleton extends Group()(_sourceInfo) { | ||
| override private[chisel3] def name = groupName | ||
| } | ||
| DynamicGroupSingleton | ||
| }) | ||
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| final implicit def group: Group = _group | ||
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| private val _cases: Map[String, Case] = caseNames.map { caseName => | ||
| caseName -> Builder.getOrCreateDynamicCase(_group, caseName, () => { | ||
| object DynamicCaseSingleton extends Case()(_group, _sourceInfo) { | ||
| override private[chisel3] def name = caseName | ||
| } | ||
| DynamicCaseSingleton | ||
| }) | ||
| }.toMap | ||
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| def cases: Map[String, Case] = _cases | ||
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| def apply(caseName: String): Case = _cases.getOrElse( | ||
| caseName, | ||
| throw new NoSuchElementException(s"Case '$caseName' not found in group '$groupName'. Available cases: ${_cases.keys.mkString(", ")}") | ||
| ) | ||
| } | ||
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| /** An option case declaration. | ||
| */ | ||
| abstract class Case(implicit val group: Group, _sourceInfo: SourceInfo) { | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,109 @@ | ||
| // SPDX-License-Identifier: Apache-2.0 | ||
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| package chiselTests | ||
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| import chisel3._ | ||
| import chisel3.choice.{Case, DynamicGroup, Group, ModuleChoice} | ||
| import chisel3.testing.scalatest.FileCheck | ||
| import circt.stage.ChiselStage | ||
| import org.scalatest.flatspec.AnyFlatSpec | ||
| import org.scalatest.matchers.should.Matchers | ||
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| class DynamicGroupSpec extends AnyFlatSpec with Matchers with FileCheck { | ||
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| class TargetIO(width: Int) extends Bundle { | ||
| val in = Flipped(UInt(width.W)) | ||
| val out = UInt(width.W) | ||
| } | ||
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| class FPGATarget extends FixedIORawModule[TargetIO](new TargetIO(8)) { | ||
| io.out := io.in | ||
| } | ||
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| class ASICTarget extends FixedIOExtModule[TargetIO](new TargetIO(8)) | ||
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| class VerifTarget extends FixedIORawModule[TargetIO](new TargetIO(8)) { | ||
| io.out := io.in | ||
| } | ||
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| it should "emit options and cases with DynamicGroup" in { | ||
| val platform = new DynamicGroup("Platform", Seq("FPGA", "ASIC")) | ||
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| class ModuleWithDynamicChoice extends Module { | ||
| val inst = ModuleChoice(new VerifTarget)(Seq( | ||
| platform("FPGA") -> new FPGATarget, | ||
| platform("ASIC") -> new ASICTarget | ||
| )) | ||
| val io = IO(inst.cloneType) | ||
| io <> inst | ||
| } | ||
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| ChiselStage | ||
| .emitCHIRRTL(new ModuleWithDynamicChoice) | ||
| .fileCheck()( | ||
| """|CHECK: option Platform : | ||
| |CHECK-NEXT: FPGA | ||
| |CHECK-NEXT: ASIC | ||
| |CHECK: instchoice inst of VerifTarget, Platform : | ||
| |CHECK-NEXT: FPGA => FPGATarget | ||
| |CHECK-NEXT: ASIC => ASICTarget""".stripMargin | ||
| ) | ||
| } | ||
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| it should "allow same DynamicGroup name to be reused" in { | ||
| class ModuleWithReusedGroup extends Module { | ||
| val platform1 = new DynamicGroup("Platform", Seq("FPGA", "ASIC")) | ||
| val platform2 = new DynamicGroup("Platform", Seq("FPGA", "ASIC")) // Should share the same group | ||
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| val inst1 = ModuleChoice(new VerifTarget)(Seq(platform1("FPGA") -> new FPGATarget)) | ||
| val inst2 = ModuleChoice(new VerifTarget)(Seq(platform2("ASIC") -> new ASICTarget)) | ||
| val io1 = IO(inst1.cloneType) | ||
| val io2 = IO(inst2.cloneType) | ||
| io1 <> inst1 | ||
| io2 <> inst2 | ||
| } | ||
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| ChiselStage | ||
| .emitCHIRRTL(new ModuleWithReusedGroup) | ||
| .fileCheck()( | ||
| """|CHECK: option Platform : | ||
| |CHECK-NEXT: FPGA | ||
| |CHECK-NEXT: ASIC | ||
| |CHECK-NOT: option Platform : | ||
| """.stripMargin | ||
| ) | ||
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| } | ||
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| it should "reject DynamicGroup with same name but different cases" in { | ||
| class ModuleWithMismatchedCases extends Module { | ||
| val platform1 = new DynamicGroup("Platform", Seq("FPGA", "ASIC")) | ||
| val platform2 = new DynamicGroup("Platform", Seq("FPGA", "GPU")) | ||
| } | ||
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| val exception = intercept[IllegalArgumentException] { | ||
| ChiselStage.emitCHIRRTL(new ModuleWithMismatchedCases) | ||
| } | ||
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| exception.getMessage should include("DynamicGroup 'Platform' already exists with different case names") | ||
| exception.getMessage should include("FPGA") | ||
| exception.getMessage should include("ASIC") | ||
| exception.getMessage should include("GPU") | ||
| } | ||
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| it should "reject DynamicGroup with same cases but different order" in { | ||
| class ModuleWithDifferentOrder extends Module { | ||
| val platform1 = new DynamicGroup("Platform", Seq("FPGA", "ASIC")) | ||
| val platform2 = new DynamicGroup("Platform", Seq("ASIC", "FPGA")) | ||
| } | ||
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| val exception = intercept[IllegalArgumentException] { | ||
| ChiselStage.emitCHIRRTL(new ModuleWithDifferentOrder) | ||
| } | ||
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| exception.getMessage should include("DynamicGroup 'Platform' already exists with different case names") | ||
| exception.getMessage should include("FPGA") | ||
| exception.getMessage should include("ASIC") | ||
| } | ||
| } | ||
|
|
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I don't love it due to the complexity, but this should probably implement the
valnaming with asuggestNamemethod like other things in Chisel.There was a problem hiding this comment.
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I think I want to disallow that level of dynamic behavior. The group name is essentially user/designer facing API even when they are generated dynamically.