Code changes to allow compatibility with Vivado 2025.2

docker/Dockerfile.finn

@@ -50,6 +50,7 @@ RUN apt-get update && \
     libsm6 \
     libxext6 \
     libxrender-dev \
+    libpixman-1-0 \
     nano \
     zsh \
     rsync \

finn_xsi/finn_xsi/adapter.py

@@ -45,7 +45,10 @@ def compile_sim_obj(top_module_name, source_list, sim_out_dir, debug=False, beha
         }
         verilog_header_incl_str = " ".join(["--include " + x for x in verilog_headers])
 
-        for src_line in source_list:
+        # sort src list so that configs are loaded first
+        pattern = "swg_pkg"
+        srcs_list = sorted(source_list, key=lambda s: (pattern not in s, s))
+        for src_line in srcs_list:
             if src_line.endswith(".v"):
                 f.write(f"verilog work {verilog_header_incl_str} {src_line}\n")
             elif src_line.endswith(".vhd"):
@@ -80,6 +83,8 @@ def compile_sim_obj(top_module_name, source_list, sim_out_dir, debug=False, beha
         "floating_point_v7_1_18",
         "floating_point_v7_1_15",
         "floating_point_v7_1_19",
+        "floating_point_v7_1_21",
+        "floating_point_v7_0_26",
     ]
 
     cmd_xelab = [

src/finn/custom_op/fpgadataflow/hlsbackend.py

@@ -26,6 +26,7 @@
 # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+import glob
 import numpy as np
 import os
 import re
@@ -60,6 +61,21 @@ def get_nodeattr_types(self):
             "hls_style": ("s", False, "ifm_aware", {"ifm_aware", "freerunning"}),
         }
 
+    def find_subcore_path(self):
+        code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
+        search_pattern = (
+            "{}/project_{}/sol1/impl/ip/subcore_prj/subcore_prj.gen/sources_1/ip/{}_*/sim/".format(
+                code_gen_dir, self.onnx_node.name, self.onnx_node.name
+            )
+        )
+
+        matching_paths = glob.glob(search_pattern)
+        if matching_paths:
+            # Return the first matching path found
+            return matching_paths
+        else:
+            return None
+
     def get_all_verilog_paths(self):
         "Return list of all folders containing Verilog code for this node."
 
@@ -72,11 +88,15 @@ def get_all_verilog_paths(self):
         subcore_verilog_path = "{}/project_{}/sol1/impl/ip/hdl/ip/".format(
             code_gen_dir, self.onnx_node.name
         )
+        subcore_vhdl_path = self.find_subcore_path()
+
         # default impl only returns the HLS verilog codegen dir and subcore (impl/ip/hdl/ip) dir
         # if it exists
         ret = [verilog_path]
         if os.path.isdir(subcore_verilog_path):
             ret += [subcore_verilog_path]
+        if subcore_vhdl_path:
+            ret += subcore_vhdl_path
         return ret
 
     def get_all_verilog_filenames(self, abspath=False):
@@ -86,7 +106,7 @@ def get_all_verilog_filenames(self, abspath=False):
         verilog_paths = self.get_all_verilog_paths()
         for verilog_path in verilog_paths:
             for f in os.listdir(verilog_path):
-                if f.endswith(".v"):
+                if f.endswith(".v") or f.endswith(".vhd"):
                     if abspath:
                         verilog_files += [verilog_path + "/" + f]
                     else:

src/finn/transformation/fpgadataflow/create_stitched_ip.py

@@ -731,7 +731,8 @@ def apply(self, model):
         tcl.append(
             "set all_v_files [get_files -filter {USED_IN_SYNTHESIS == 1 "
             + "&& (FILE_TYPE == Verilog || FILE_TYPE == SystemVerilog "
-            + '|| FILE_TYPE =="Verilog Header" || FILE_TYPE == XCI)}]'
+            + '|| FILE_TYPE == "Verilog Header" || FILE_TYPE == VHDL '
+            + "|| FILE_TYPE == XCI)}]"
         )
         v_file_list = "%s/all_verilog_srcs.txt" % vivado_stitch_proj_dir
         tcl.append("set fp [open %s w]" % v_file_list)