From a0f9a15b4a916c92d51131418e9fe080c83f9d3c Mon Sep 17 00:00:00 2001 From: Andreas Liljeqvist Date: Sat, 17 Jan 2026 11:36:25 +0100 Subject: [PATCH 01/18] Fix is_ascii performance regression on AVX-512 CPUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When `[u8]::is_ascii()` is compiled with `-C target-cpu=native` on AVX-512 CPUs, LLVM generates inefficient code. Because `is_ascii` is marked `#[inline]`, it gets inlined and recompiled with the user's target settings. The previous implementation used a counting loop that LLVM auto-vectorizes to `pmovmskb` on SSE2, but with AVX-512 enabled, LLVM uses k-registers and extracts bits individually with ~31 `kshiftrd` instructions. This fix replaces the counting loop with explicit SSE2 intrinsics (`_mm_loadu_si128`, `_mm_or_si128`, `_mm_movemask_epi8`) for x86_64. `_mm_movemask_epi8` compiles to `pmovmskb`, forcing efficient codegen regardless of CPU features. Benchmark results on AMD Ryzen 5 7500F (Zen 4 with AVX-512): - Default build: ~73 GB/s → ~74 GB/s (no regression) - With -C target-cpu=native: ~3 GB/s → ~67 GB/s (22x improvement) The loongarch64 implementation retains the original counting loop since it doesn't have this issue. Regression from: https://github.com/rust-lang/rust/pull/130733 --- library/core/src/slice/ascii.rs | 86 +++++++++++++++++--- tests/assembly-llvm/slice-is-ascii-avx512.rs | 18 ++++ tests/codegen-llvm/slice-is-ascii.rs | 9 +- 3 files changed, 98 insertions(+), 15 deletions(-) create mode 100644 tests/assembly-llvm/slice-is-ascii-avx512.rs diff --git a/library/core/src/slice/ascii.rs b/library/core/src/slice/ascii.rs index 3e8c553f9f159..c9e168d6cbf83 100644 --- a/library/core/src/slice/ascii.rs +++ b/library/core/src/slice/ascii.rs @@ -3,10 +3,7 @@ use core::ascii::EscapeDefault; use crate::fmt::{self, Write}; -#[cfg(not(any( - all(target_arch = "x86_64", target_feature = "sse2"), - all(target_arch = "loongarch64", target_feature = "lsx") -)))] +#[cfg(not(all(target_arch = "loongarch64", target_feature = "lsx")))] use crate::intrinsics::const_eval_select; use crate::{ascii, iter, ops}; @@ -463,19 +460,84 @@ const fn is_ascii(s: &[u8]) -> bool { ) } -/// ASCII test optimized to use the `pmovmskb` instruction on `x86-64` and the -/// `vmskltz.b` instruction on `loongarch64`. +/// SSE2 implementation using `_mm_movemask_epi8` (compiles to `pmovmskb`) to +/// avoid LLVM's broken AVX-512 auto-vectorization of counting loops. +/// +/// # Safety +/// Requires SSE2 support (guaranteed on x86_64). +#[cfg(all(target_arch = "x86_64", target_feature = "sse2"))] +#[target_feature(enable = "sse2")] +unsafe fn is_ascii_sse2(bytes: &[u8]) -> bool { + use crate::arch::x86_64::{__m128i, _mm_loadu_si128, _mm_movemask_epi8, _mm_or_si128}; + + const CHUNK_SIZE: usize = 32; + + let mut i = 0; + + while i + CHUNK_SIZE <= bytes.len() { + // SAFETY: We have verified that `i + CHUNK_SIZE <= bytes.len()`. + let ptr = unsafe { bytes.as_ptr().add(i) }; + + // Load two 16-byte chunks and combine them. + // SAFETY: We verified `i + 32 <= len`, so ptr is valid for 32 bytes. + // `_mm_loadu_si128` allows unaligned loads. + let chunk1 = unsafe { _mm_loadu_si128(ptr as *const __m128i) }; + // SAFETY: Same as above - ptr.add(16) is within the valid 32-byte range. + let chunk2 = unsafe { _mm_loadu_si128(ptr.add(16) as *const __m128i) }; + + // OR them together - if any byte has the high bit set, the result will too + let combined = _mm_or_si128(chunk1, chunk2); + + // Create a mask from the MSBs of each byte. + // If any byte is >= 128, its MSB is 1, so the mask will be non-zero. + let mask = _mm_movemask_epi8(combined); + + if mask != 0 { + return false; + } + + i += CHUNK_SIZE; + } + + // Handle remaining bytes with simple loop + while i < bytes.len() { + if !bytes[i].is_ascii() { + return false; + } + i += 1; + } + + true +} + +/// ASCII test optimized to use the `pmovmskb` instruction on `x86-64`. +/// +/// Uses explicit SSE2 intrinsics to prevent LLVM from auto-vectorizing with +/// broken AVX-512 code that extracts mask bits one-by-one. +#[cfg(all(target_arch = "x86_64", target_feature = "sse2"))] +#[inline] +#[rustc_allow_const_fn_unstable(const_eval_select)] +const fn is_ascii(bytes: &[u8]) -> bool { + const_eval_select!( + @capture { bytes: &[u8] } -> bool: + if const { + is_ascii_simple(bytes) + } else { + // SAFETY: SSE2 is guaranteed available on x86_64 + unsafe { is_ascii_sse2(bytes) } + } + ) +} + +/// ASCII test optimized to use the `vmskltz.b` instruction on `loongarch64`. /// /// Other platforms are not likely to benefit from this code structure, so they /// use SWAR techniques to test for ASCII in `usize`-sized chunks. -#[cfg(any( - all(target_arch = "x86_64", target_feature = "sse2"), - all(target_arch = "loongarch64", target_feature = "lsx") -))] +#[cfg(all(target_arch = "loongarch64", target_feature = "lsx"))] #[inline] const fn is_ascii(bytes: &[u8]) -> bool { // Process chunks of 32 bytes at a time in the fast path to enable - // auto-vectorization and use of `pmovmskb`. Two 128-bit vector registers + // auto-vectorization and use of `vmskltz.b`. Two 128-bit vector registers // can be OR'd together and then the resulting vector can be tested for // non-ASCII bytes. const CHUNK_SIZE: usize = 32; @@ -485,7 +547,7 @@ const fn is_ascii(bytes: &[u8]) -> bool { while i + CHUNK_SIZE <= bytes.len() { let chunk_end = i + CHUNK_SIZE; - // Get LLVM to produce a `pmovmskb` instruction on x86-64 which + // Get LLVM to produce a `vmskltz.b` instruction on loongarch64 which // creates a mask from the most significant bit of each byte. // ASCII bytes are less than 128 (0x80), so their most significant // bit is unset. diff --git a/tests/assembly-llvm/slice-is-ascii-avx512.rs b/tests/assembly-llvm/slice-is-ascii-avx512.rs new file mode 100644 index 0000000000000..d3a441fec96cb --- /dev/null +++ b/tests/assembly-llvm/slice-is-ascii-avx512.rs @@ -0,0 +1,18 @@ +//@ only-x86_64 +//@ compile-flags: -C opt-level=3 -C target-cpu=znver4 +//@ compile-flags: -C llvm-args=-x86-asm-syntax=intel +//@ assembly-output: emit-asm +#![crate_type = "lib"] + +// Verify is_ascii uses pmovmskb/vpmovmskb instead of kshiftrd with AVX-512. +// The fix uses explicit SSE2 intrinsics to avoid LLVM's broken auto-vectorization. +// +// See: https://github.com/rust-lang/rust/issues/129293 + +// CHECK-LABEL: test_is_ascii +#[no_mangle] +pub fn test_is_ascii(s: &[u8]) -> bool { + // CHECK-NOT: kshiftrd + // CHECK-NOT: kshiftrq + s.is_ascii() +} diff --git a/tests/codegen-llvm/slice-is-ascii.rs b/tests/codegen-llvm/slice-is-ascii.rs index 67537c871a0a3..1f41b69e43966 100644 --- a/tests/codegen-llvm/slice-is-ascii.rs +++ b/tests/codegen-llvm/slice-is-ascii.rs @@ -1,10 +1,13 @@ -//@ only-x86_64 -//@ compile-flags: -C opt-level=3 -C target-cpu=x86-64 +//@ only-loongarch64 +//@ compile-flags: -C opt-level=3 #![crate_type = "lib"] -/// Check that the fast-path of `is_ascii` uses a `pmovmskb` instruction. +/// Check that the fast-path of `is_ascii` uses a `vmskltz.b` instruction. /// Platforms lacking an equivalent instruction use other techniques for /// optimizing `is_ascii`. +/// +/// Note: x86_64 uses explicit SSE2 intrinsics instead of relying on +/// auto-vectorization. See `slice-is-ascii-avx512.rs`. // CHECK-LABEL: @is_ascii_autovectorized #[no_mangle] pub fn is_ascii_autovectorized(s: &[u8]) -> bool { From 08432c892758a06a6bab9fa0584effb7e7881303 Mon Sep 17 00:00:00 2001 From: Andreas Liljeqvist Date: Sun, 18 Jan 2026 22:49:37 +0100 Subject: [PATCH 02/18] Optimize small input path for is_ascii on x86_64 For inputs smaller than 32 bytes, use usize-at-a-time processing instead of calling the SSE2 function. This avoids function call overhead from #[target_feature(enable = "sse2")] which prevents inlining. Also moves CHUNK_SIZE to module level so it can be shared between is_ascii and is_ascii_sse2. --- library/core/src/slice/ascii.rs | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/library/core/src/slice/ascii.rs b/library/core/src/slice/ascii.rs index c9e168d6cbf83..25b8a10af3555 100644 --- a/library/core/src/slice/ascii.rs +++ b/library/core/src/slice/ascii.rs @@ -460,6 +460,10 @@ const fn is_ascii(s: &[u8]) -> bool { ) } +/// Chunk size for vectorized ASCII checking (two 16-byte SSE registers). +#[cfg(all(target_arch = "x86_64", target_feature = "sse2"))] +const CHUNK_SIZE: usize = 32; + /// SSE2 implementation using `_mm_movemask_epi8` (compiles to `pmovmskb`) to /// avoid LLVM's broken AVX-512 auto-vectorization of counting loops. /// @@ -470,8 +474,6 @@ const fn is_ascii(s: &[u8]) -> bool { unsafe fn is_ascii_sse2(bytes: &[u8]) -> bool { use crate::arch::x86_64::{__m128i, _mm_loadu_si128, _mm_movemask_epi8, _mm_or_si128}; - const CHUNK_SIZE: usize = 32; - let mut i = 0; while i + CHUNK_SIZE <= bytes.len() { @@ -518,11 +520,27 @@ unsafe fn is_ascii_sse2(bytes: &[u8]) -> bool { #[inline] #[rustc_allow_const_fn_unstable(const_eval_select)] const fn is_ascii(bytes: &[u8]) -> bool { + const USIZE_SIZE: usize = size_of::(); + const NONASCII_MASK: usize = usize::MAX / 255 * 0x80; + const_eval_select!( @capture { bytes: &[u8] } -> bool: if const { is_ascii_simple(bytes) } else { + // For small inputs, use usize-at-a-time processing to avoid SSE2 call overhead. + if bytes.len() < CHUNK_SIZE { + let chunks = bytes.chunks_exact(USIZE_SIZE); + let remainder = chunks.remainder(); + for chunk in chunks { + let word = usize::from_ne_bytes(chunk.try_into().unwrap()); + if (word & NONASCII_MASK) != 0 { + return false; + } + } + return remainder.iter().all(|b| b.is_ascii()); + } + // SAFETY: SSE2 is guaranteed available on x86_64 unsafe { is_ascii_sse2(bytes) } } From 8c1e51f8f9c74f93c9c25dd64a8e08a7c6ce6adc Mon Sep 17 00:00:00 2001 From: Brian Cain Date: Thu, 22 Jan 2026 11:12:13 -0600 Subject: [PATCH 03/18] hexagon: Add HVX target features This will be used in order to emit HVX intrinsics --- compiler/rustc_target/src/target_features.rs | 17 ++++++++++++++++- tests/ui/check-cfg/target_feature.stderr | 15 +++++++++++++++ 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/compiler/rustc_target/src/target_features.rs b/compiler/rustc_target/src/target_features.rs index 4eba426dda59f..fde7dfcabb701 100644 --- a/compiler/rustc_target/src/target_features.rs +++ b/compiler/rustc_target/src/target_features.rs @@ -492,7 +492,22 @@ static X86_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[ const HEXAGON_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[ // tidy-alphabetical-start ("hvx", Unstable(sym::hexagon_target_feature), &[]), + ("hvx-ieee-fp", Unstable(sym::hexagon_target_feature), &["hvx"]), + ("hvx-length64b", Unstable(sym::hexagon_target_feature), &["hvx"]), ("hvx-length128b", Unstable(sym::hexagon_target_feature), &["hvx"]), + ("hvx-qfloat", Unstable(sym::hexagon_target_feature), &["hvx"]), + ("hvxv60", Unstable(sym::hexagon_target_feature), &["hvx"]), + ("hvxv62", Unstable(sym::hexagon_target_feature), &["hvxv60"]), + ("hvxv65", Unstable(sym::hexagon_target_feature), &["hvxv62"]), + ("hvxv66", Unstable(sym::hexagon_target_feature), &["hvxv65", "zreg"]), + ("hvxv67", Unstable(sym::hexagon_target_feature), &["hvxv66"]), + ("hvxv68", Unstable(sym::hexagon_target_feature), &["hvxv67"]), + ("hvxv69", Unstable(sym::hexagon_target_feature), &["hvxv68"]), + ("hvxv71", Unstable(sym::hexagon_target_feature), &["hvxv69"]), + ("hvxv73", Unstable(sym::hexagon_target_feature), &["hvxv71"]), + ("hvxv75", Unstable(sym::hexagon_target_feature), &["hvxv73"]), + ("hvxv79", Unstable(sym::hexagon_target_feature), &["hvxv75"]), + ("zreg", Unstable(sym::hexagon_target_feature), &[]), // tidy-alphabetical-end ]; @@ -949,7 +964,7 @@ const SPARC_FEATURES_FOR_CORRECT_FIXED_LENGTH_VECTOR_ABI: &'static [(u64, &'stat &[/*(64, "vis")*/]; const HEXAGON_FEATURES_FOR_CORRECT_FIXED_LENGTH_VECTOR_ABI: &'static [(u64, &'static str)] = - &[/*(512, "hvx-length64b"),*/ (1024, "hvx-length128b")]; + &[(512, "hvx-length64b"), (1024, "hvx-length128b")]; const MIPS_FEATURES_FOR_CORRECT_FIXED_LENGTH_VECTOR_ABI: &'static [(u64, &'static str)] = &[(128, "msa")]; const CSKY_FEATURES_FOR_CORRECT_FIXED_LENGTH_VECTOR_ABI: &'static [(u64, &'static str)] = diff --git a/tests/ui/check-cfg/target_feature.stderr b/tests/ui/check-cfg/target_feature.stderr index 6125e66320c8a..89123c9100825 100644 --- a/tests/ui/check-cfg/target_feature.stderr +++ b/tests/ui/check-cfg/target_feature.stderr @@ -131,7 +131,21 @@ LL | cfg!(target_feature = "_UNEXPECTED_VALUE"); `high-registers` `high-word` `hvx` +`hvx-ieee-fp` `hvx-length128b` +`hvx-length64b` +`hvx-qfloat` +`hvxv60` +`hvxv62` +`hvxv65` +`hvxv66` +`hvxv67` +`hvxv68` +`hvxv69` +`hvxv71` +`hvxv73` +`hvxv75` +`hvxv79` `hwdiv` `i8mm` `isa-68000` @@ -431,6 +445,7 @@ LL | cfg!(target_feature = "_UNEXPECTED_VALUE"); `zksed` `zksh` `zkt` +`zreg` `ztso` `zvbb` `zvbc` From 5dd7c0b5aba324bf127e07bf1406926b329b031b Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Wed, 31 Dec 2025 21:49:48 +0000 Subject: [PATCH 04/18] Rationalise the Armv7-A, Armv7-R and Armv8-R bare-metal target configs --- .../src/spec/targets/armv7a_none_eabi.rs | 45 +++++-------------- .../src/spec/targets/armv7a_none_eabihf.rs | 37 +++++---------- .../src/spec/targets/armv7r_none_eabi.rs | 17 ++----- .../src/spec/targets/armv7r_none_eabihf.rs | 17 ++----- .../src/spec/targets/armv8r_none_eabihf.rs | 14 +----- 5 files changed, 28 insertions(+), 102 deletions(-) diff --git a/compiler/rustc_target/src/spec/targets/armv7a_none_eabi.rs b/compiler/rustc_target/src/spec/targets/armv7a_none_eabi.rs index 6b7707a47390a..e8c5c16d8eb5e 100644 --- a/compiler/rustc_target/src/spec/targets/armv7a_none_eabi.rs +++ b/compiler/rustc_target/src/spec/targets/armv7a_none_eabi.rs @@ -1,40 +1,8 @@ -// Generic ARMv7-A target for bare-metal code - floating point disabled -// -// This is basically the `armv7-unknown-linux-gnueabi` target with some changes -// (listed below) to bring it closer to the bare-metal `thumb` & `aarch64` -// targets: -// -// - `TargetOptions.features`: added `+strict-align`. rationale: unaligned -// memory access is disabled on boot on these cores -// - linker changed to LLD. rationale: C is not strictly needed to build -// bare-metal binaries (the `gcc` linker has the advantage that it knows where C -// libraries and crt*.o are but it's not much of an advantage here); LLD is also -// faster -// - `panic_strategy` set to `abort`. rationale: matches `thumb` targets -// - `relocation-model` set to `static`; also no PIE, no relro and no dynamic -// linking. rationale: matches `thumb` targets +// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A) -use crate::spec::{ - Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata, - TargetOptions, -}; +use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base}; pub(crate) fn target() -> Target { - let opts = TargetOptions { - abi: Abi::Eabi, - llvm_floatabi: Some(FloatAbi::Soft), - linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes), - linker: Some("rust-lld".into()), - features: "+v7,+thumb2,+soft-float,-neon,+strict-align".into(), - relocation_model: RelocModel::Static, - disable_redzone: true, - max_atomic_width: Some(64), - panic_strategy: PanicStrategy::Abort, - emit_debug_gdb_scripts: false, - c_enum_min_bits: Some(8), - has_thumb_interworking: true, - ..Default::default() - }; Target { llvm_target: "armv7a-none-eabi".into(), metadata: TargetMetadata { @@ -46,6 +14,13 @@ pub(crate) fn target() -> Target { pointer_width: 32, data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), arch: Arch::Arm, - options: opts, + options: TargetOptions { + abi: Abi::Eabi, + llvm_floatabi: Some(FloatAbi::Soft), + features: "+soft-float,-neon,+strict-align".into(), + max_atomic_width: Some(64), + has_thumb_interworking: true, + ..base::arm_none::opts() + }, } } diff --git a/compiler/rustc_target/src/spec/targets/armv7a_none_eabihf.rs b/compiler/rustc_target/src/spec/targets/armv7a_none_eabihf.rs index 993390543b96d..32a79e346adcf 100644 --- a/compiler/rustc_target/src/spec/targets/armv7a_none_eabihf.rs +++ b/compiler/rustc_target/src/spec/targets/armv7a_none_eabihf.rs @@ -1,32 +1,8 @@ -// Generic ARMv7-A target for bare-metal code - floating point enabled (assumes -// FPU is present and emits FPU instructions) -// -// This is basically the `armv7-unknown-linux-gnueabihf` target with some -// changes (list in `armv7a_none_eabi.rs`) to bring it closer to the bare-metal -// `thumb` & `aarch64` targets. +// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A) -use crate::spec::{ - Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata, - TargetOptions, -}; +use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base}; pub(crate) fn target() -> Target { - let opts = TargetOptions { - abi: Abi::EabiHf, - llvm_floatabi: Some(FloatAbi::Hard), - linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes), - linker: Some("rust-lld".into()), - features: "+v7,+vfp3d16,+thumb2,-neon,+strict-align".into(), - relocation_model: RelocModel::Static, - disable_redzone: true, - max_atomic_width: Some(64), - panic_strategy: PanicStrategy::Abort, - emit_debug_gdb_scripts: false, - // GCC defaults to 8 for arm-none here. - c_enum_min_bits: Some(8), - has_thumb_interworking: true, - ..Default::default() - }; Target { llvm_target: "armv7a-none-eabihf".into(), metadata: TargetMetadata { @@ -38,6 +14,13 @@ pub(crate) fn target() -> Target { pointer_width: 32, data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), arch: Arch::Arm, - options: opts, + options: TargetOptions { + abi: Abi::EabiHf, + llvm_floatabi: Some(FloatAbi::Hard), + features: "+vfp3d16,-neon,+strict-align".into(), + max_atomic_width: Some(64), + has_thumb_interworking: true, + ..base::arm_none::opts() + }, } } diff --git a/compiler/rustc_target/src/spec/targets/armv7r_none_eabi.rs b/compiler/rustc_target/src/spec/targets/armv7r_none_eabi.rs index 551cbf4a589fa..114b079f360b7 100644 --- a/compiler/rustc_target/src/spec/targets/armv7r_none_eabi.rs +++ b/compiler/rustc_target/src/spec/targets/armv7r_none_eabi.rs @@ -1,15 +1,12 @@ // Targets the Little-endian Cortex-R4/R5 processor (ARMv7-R) -use crate::spec::{ - Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata, - TargetOptions, -}; +use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base}; pub(crate) fn target() -> Target { Target { llvm_target: "armv7r-none-eabi".into(), metadata: TargetMetadata { - description: Some("Armv7-R".into()), + description: Some("Bare Armv7-R".into()), tier: Some(2), host_tools: Some(false), std: Some(false), @@ -17,20 +14,12 @@ pub(crate) fn target() -> Target { pointer_width: 32, data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), arch: Arch::Arm, - options: TargetOptions { abi: Abi::Eabi, llvm_floatabi: Some(FloatAbi::Soft), - linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes), - linker: Some("rust-lld".into()), - relocation_model: RelocModel::Static, - panic_strategy: PanicStrategy::Abort, max_atomic_width: Some(64), - emit_debug_gdb_scripts: false, - // GCC defaults to 8 for arm-none here. - c_enum_min_bits: Some(8), has_thumb_interworking: true, - ..Default::default() + ..base::arm_none::opts() }, } } diff --git a/compiler/rustc_target/src/spec/targets/armv7r_none_eabihf.rs b/compiler/rustc_target/src/spec/targets/armv7r_none_eabihf.rs index 97c911ec80909..1c6114f9fc83a 100644 --- a/compiler/rustc_target/src/spec/targets/armv7r_none_eabihf.rs +++ b/compiler/rustc_target/src/spec/targets/armv7r_none_eabihf.rs @@ -1,15 +1,12 @@ // Targets the Little-endian Cortex-R4F/R5F processor (ARMv7-R) -use crate::spec::{ - Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata, - TargetOptions, -}; +use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base}; pub(crate) fn target() -> Target { Target { llvm_target: "armv7r-none-eabihf".into(), metadata: TargetMetadata { - description: Some("Armv7-R, hardfloat".into()), + description: Some("Bare Armv7-R, hardfloat".into()), tier: Some(2), host_tools: Some(false), std: Some(false), @@ -17,21 +14,13 @@ pub(crate) fn target() -> Target { pointer_width: 32, data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), arch: Arch::Arm, - options: TargetOptions { abi: Abi::EabiHf, llvm_floatabi: Some(FloatAbi::Hard), - linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes), - linker: Some("rust-lld".into()), - relocation_model: RelocModel::Static, - panic_strategy: PanicStrategy::Abort, features: "+vfp3d16".into(), max_atomic_width: Some(64), - emit_debug_gdb_scripts: false, - // GCC defaults to 8 for arm-none here. - c_enum_min_bits: Some(8), has_thumb_interworking: true, - ..Default::default() + ..base::arm_none::opts() }, } } diff --git a/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs b/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs index e36240b9c2234..16006e4c52cfb 100644 --- a/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs +++ b/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs @@ -1,9 +1,6 @@ // Targets the Little-endian Cortex-R52 processor (ARMv8-R) -use crate::spec::{ - Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata, - TargetOptions, -}; +use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base}; pub(crate) fn target() -> Target { Target { @@ -21,10 +18,6 @@ pub(crate) fn target() -> Target { options: TargetOptions { abi: Abi::EabiHf, llvm_floatabi: Some(FloatAbi::Hard), - linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes), - linker: Some("rust-lld".into()), - relocation_model: RelocModel::Static, - panic_strategy: PanicStrategy::Abort, // Armv8-R requires a minimum set of floating-point features equivalent to: // fp-armv8, SP-only, with 16 DP (32 SP) registers // LLVM defines Armv8-R to include these features automatically. @@ -36,11 +29,8 @@ pub(crate) fn target() -> Target { // Arm Cortex-R52 Processor Technical Reference Manual // - Chapter 15 Advanced SIMD and floating-point support max_atomic_width: Some(64), - emit_debug_gdb_scripts: false, - // GCC defaults to 8 for arm-none here. - c_enum_min_bits: Some(8), has_thumb_interworking: true, - ..Default::default() + ..base::arm_none::opts() }, } } From 96647dde7752334ac9a2137ffca9cc4f909ceee8 Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Wed, 31 Dec 2025 21:52:36 +0000 Subject: [PATCH 05/18] Add Thumb-mode targets for Armv7-R, Armv7-A and Armv8-R. --- compiler/rustc_target/src/spec/mod.rs | 5 +++ .../src/spec/targets/thumbv7a_none_eabi.rs | 26 ++++++++++++++ .../src/spec/targets/thumbv7a_none_eabihf.rs | 26 ++++++++++++++ .../src/spec/targets/thumbv7r_none_eabi.rs | 25 +++++++++++++ .../src/spec/targets/thumbv7r_none_eabihf.rs | 26 ++++++++++++++ .../src/spec/targets/thumbv8r_none_eabihf.rs | 36 +++++++++++++++++++ src/bootstrap/src/core/sanity.rs | 5 +++ src/doc/rustc/src/platform-support.md | 9 +++-- .../src/platform-support/armv7a-none-eabi.md | 10 +++--- .../src/platform-support/armv7r-none-eabi.md | 8 +++-- .../platform-support/armv8r-none-eabihf.md | 10 +++--- tests/assembly-llvm/targets/targets-elf.rs | 15 ++++++++ 12 files changed, 188 insertions(+), 13 deletions(-) create mode 100644 compiler/rustc_target/src/spec/targets/thumbv7a_none_eabi.rs create mode 100644 compiler/rustc_target/src/spec/targets/thumbv7a_none_eabihf.rs create mode 100644 compiler/rustc_target/src/spec/targets/thumbv7r_none_eabi.rs create mode 100644 compiler/rustc_target/src/spec/targets/thumbv7r_none_eabihf.rs create mode 100644 compiler/rustc_target/src/spec/targets/thumbv8r_none_eabihf.rs diff --git a/compiler/rustc_target/src/spec/mod.rs b/compiler/rustc_target/src/spec/mod.rs index ef475630d4943..c5a7f119118c9 100644 --- a/compiler/rustc_target/src/spec/mod.rs +++ b/compiler/rustc_target/src/spec/mod.rs @@ -1596,8 +1596,11 @@ supported_targets! { ("armebv7r-none-eabi", armebv7r_none_eabi), ("armebv7r-none-eabihf", armebv7r_none_eabihf), ("armv7r-none-eabi", armv7r_none_eabi), + ("thumbv7r-none-eabi", thumbv7r_none_eabi), ("armv7r-none-eabihf", armv7r_none_eabihf), + ("thumbv7r-none-eabihf", thumbv7r_none_eabihf), ("armv8r-none-eabihf", armv8r_none_eabihf), + ("thumbv8r-none-eabihf", thumbv8r_none_eabihf), ("armv7-rtems-eabihf", armv7_rtems_eabihf), @@ -1649,7 +1652,9 @@ supported_targets! { ("thumbv8m.main-none-eabihf", thumbv8m_main_none_eabihf), ("armv7a-none-eabi", armv7a_none_eabi), + ("thumbv7a-none-eabi", thumbv7a_none_eabi), ("armv7a-none-eabihf", armv7a_none_eabihf), + ("thumbv7a-none-eabihf", thumbv7a_none_eabihf), ("armv7a-nuttx-eabi", armv7a_nuttx_eabi), ("armv7a-nuttx-eabihf", armv7a_nuttx_eabihf), ("armv7a-vex-v5", armv7a_vex_v5), diff --git a/compiler/rustc_target/src/spec/targets/thumbv7a_none_eabi.rs b/compiler/rustc_target/src/spec/targets/thumbv7a_none_eabi.rs new file mode 100644 index 0000000000000..ce11e3f0875c9 --- /dev/null +++ b/compiler/rustc_target/src/spec/targets/thumbv7a_none_eabi.rs @@ -0,0 +1,26 @@ +// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A) + +use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base}; + +pub(crate) fn target() -> Target { + Target { + llvm_target: "thumbv7a-none-eabi".into(), + metadata: TargetMetadata { + description: Some("Thumb-mode Bare Armv7-A".into()), + tier: Some(2), + host_tools: Some(false), + std: Some(false), + }, + pointer_width: 32, + data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), + arch: Arch::Arm, + options: TargetOptions { + abi: Abi::Eabi, + llvm_floatabi: Some(FloatAbi::Soft), + features: "+soft-float,-neon,+strict-align".into(), + max_atomic_width: Some(64), + has_thumb_interworking: true, + ..base::arm_none::opts() + }, + } +} diff --git a/compiler/rustc_target/src/spec/targets/thumbv7a_none_eabihf.rs b/compiler/rustc_target/src/spec/targets/thumbv7a_none_eabihf.rs new file mode 100644 index 0000000000000..12210e9c2b014 --- /dev/null +++ b/compiler/rustc_target/src/spec/targets/thumbv7a_none_eabihf.rs @@ -0,0 +1,26 @@ +// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A) + +use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base}; + +pub(crate) fn target() -> Target { + Target { + llvm_target: "thumbv7a-none-eabihf".into(), + metadata: TargetMetadata { + description: Some("Thumb-mode Bare Armv7-A, hardfloat".into()), + tier: Some(2), + host_tools: Some(false), + std: Some(false), + }, + pointer_width: 32, + data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), + arch: Arch::Arm, + options: TargetOptions { + abi: Abi::EabiHf, + llvm_floatabi: Some(FloatAbi::Hard), + features: "+vfp3d16,-neon,+strict-align".into(), + max_atomic_width: Some(64), + has_thumb_interworking: true, + ..base::arm_none::opts() + }, + } +} diff --git a/compiler/rustc_target/src/spec/targets/thumbv7r_none_eabi.rs b/compiler/rustc_target/src/spec/targets/thumbv7r_none_eabi.rs new file mode 100644 index 0000000000000..bf71d31a06ecf --- /dev/null +++ b/compiler/rustc_target/src/spec/targets/thumbv7r_none_eabi.rs @@ -0,0 +1,25 @@ +// Targets the Little-endian Cortex-R4/R5 processor (ARMv7-R) + +use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base}; + +pub(crate) fn target() -> Target { + Target { + llvm_target: "thumbv7r-none-eabi".into(), + metadata: TargetMetadata { + description: Some("Thumb-mode Bare Armv7-R".into()), + tier: Some(2), + host_tools: Some(false), + std: Some(false), + }, + pointer_width: 32, + data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), + arch: Arch::Arm, + options: TargetOptions { + abi: Abi::Eabi, + llvm_floatabi: Some(FloatAbi::Soft), + max_atomic_width: Some(64), + has_thumb_interworking: true, + ..base::arm_none::opts() + }, + } +} diff --git a/compiler/rustc_target/src/spec/targets/thumbv7r_none_eabihf.rs b/compiler/rustc_target/src/spec/targets/thumbv7r_none_eabihf.rs new file mode 100644 index 0000000000000..88b5e67644035 --- /dev/null +++ b/compiler/rustc_target/src/spec/targets/thumbv7r_none_eabihf.rs @@ -0,0 +1,26 @@ +// Targets the Little-endian Cortex-R4F/R5F processor (ARMv7-R) + +use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base}; + +pub(crate) fn target() -> Target { + Target { + llvm_target: "thumbv7r-none-eabihf".into(), + metadata: TargetMetadata { + description: Some("Thumb-mode Bare Armv7-R, hardfloat".into()), + tier: Some(2), + host_tools: Some(false), + std: Some(false), + }, + pointer_width: 32, + data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), + arch: Arch::Arm, + options: TargetOptions { + abi: Abi::EabiHf, + llvm_floatabi: Some(FloatAbi::Hard), + features: "+vfp3d16".into(), + max_atomic_width: Some(64), + has_thumb_interworking: true, + ..base::arm_none::opts() + }, + } +} diff --git a/compiler/rustc_target/src/spec/targets/thumbv8r_none_eabihf.rs b/compiler/rustc_target/src/spec/targets/thumbv8r_none_eabihf.rs new file mode 100644 index 0000000000000..87434cd7353c0 --- /dev/null +++ b/compiler/rustc_target/src/spec/targets/thumbv8r_none_eabihf.rs @@ -0,0 +1,36 @@ +// Targets the Little-endian Cortex-R52 processor (ARMv8-R) + +use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base}; + +pub(crate) fn target() -> Target { + Target { + llvm_target: "thumbv8r-none-eabihf".into(), + metadata: TargetMetadata { + description: Some("Thumb-mode Bare Armv8-R, hardfloat".into()), + tier: Some(2), + host_tools: Some(false), + std: Some(false), + }, + pointer_width: 32, + data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), + arch: Arch::Arm, + + options: TargetOptions { + abi: Abi::EabiHf, + llvm_floatabi: Some(FloatAbi::Hard), + // Armv8-R requires a minimum set of floating-point features equivalent to: + // fp-armv8, SP-only, with 16 DP (32 SP) registers + // LLVM defines Armv8-R to include these features automatically. + // + // The Cortex-R52 supports these default features and optionally includes: + // neon-fp-armv8, SP+DP, with 32 DP registers + // + // Reference: + // Arm Cortex-R52 Processor Technical Reference Manual + // - Chapter 15 Advanced SIMD and floating-point support + max_atomic_width: Some(64), + has_thumb_interworking: true, + ..base::arm_none::opts() + }, + } +} diff --git a/src/bootstrap/src/core/sanity.rs b/src/bootstrap/src/core/sanity.rs index 607b9a384d196..235bbf8ddb783 100644 --- a/src/bootstrap/src/core/sanity.rs +++ b/src/bootstrap/src/core/sanity.rs @@ -38,6 +38,11 @@ pub struct Finder { const STAGE0_MISSING_TARGETS: &[&str] = &[ // just a dummy comment so the list doesn't get onelined "x86_64-unknown-linux-gnuasan", + "thumbv7a-none-eabi", + "thumbv7a-none-eabihf", + "thumbv7r-none-eabi", + "thumbv7r-none-eabihf", + "thumbv8r-none-eabihf", ]; /// Minimum version threshold for libstdc++ required when using prebuilt LLVM diff --git a/src/doc/rustc/src/platform-support.md b/src/doc/rustc/src/platform-support.md index 889f96f5fefab..9362c8b98fe3d 100644 --- a/src/doc/rustc/src/platform-support.md +++ b/src/doc/rustc/src/platform-support.md @@ -411,17 +411,22 @@ target | std | host | notes [`thumbv4t-none-eabi`](platform-support/armv4t-none-eabi.md) | * | | Thumb-mode Bare Armv4T [`thumbv5te-none-eabi`](platform-support/armv5te-none-eabi.md) | * | | Thumb-mode Bare Armv5TE [`thumbv6m-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv6M with NuttX -`thumbv7a-pc-windows-msvc` | | | -[`thumbv7a-uwp-windows-msvc`](platform-support/uwp-windows-msvc.md) | | | +[`thumbv7a-none-eabi`](platform-support/armv7a-none-eabi.md) | * | | Thumb-mode Bare Armv7-A +[`thumbv7a-none-eabihf`](platform-support/armv7a-none-eabi.md) | * | | Thumb-mode Bare Armv7-A, hardfloat [`thumbv7a-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv7-A with NuttX [`thumbv7a-nuttx-eabihf`](platform-support/nuttx.md) | ✓ | | ARMv7-A with NuttX, hardfloat +`thumbv7a-pc-windows-msvc` | | | +[`thumbv7a-uwp-windows-msvc`](platform-support/uwp-windows-msvc.md) | | | [`thumbv7em-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv7EM with NuttX [`thumbv7em-nuttx-eabihf`](platform-support/nuttx.md) | ✓ | | ARMv7EM with NuttX, hardfloat [`thumbv7m-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv7M with NuttX `thumbv7neon-unknown-linux-musleabihf` | ? | | Thumb2-mode Armv7-A Linux with NEON, musl 1.2.5 +[`thumbv7r-none-eabi`](platform-support/armv7r-none-eabi.md) | * | | Thumb-mode Bare Armv7-R +[`thumbv7r-none-eabihf`](platform-support/armv7r-none-eabi.md) | * | | Thumb-mode Bare Armv7-R, hardfloat [`thumbv8m.base-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv8M Baseline with NuttX [`thumbv8m.main-nuttx-eabi`](platform-support/nuttx.md) | ✓ | | ARMv8M Mainline with NuttX [`thumbv8m.main-nuttx-eabihf`](platform-support/nuttx.md) | ✓ | | ARMv8M Mainline with NuttX, hardfloat +[`thumbv8r-none-eabihf`](platform-support/armv8r-none-eabihf.md) | * | | Thumb-mode Bare Armv8-R, hardfloat [`wasm64-unknown-unknown`](platform-support/wasm64-unknown-unknown.md) | ? | | WebAssembly [`wasm32-wali-linux-musl`](platform-support/wasm32-wali-linux.md) | ? | | WebAssembly with [WALI](https://github.com/arjunr2/WALI) [`wasm32-wasip3`](platform-support/wasm32-wasip3.md) | ✓ | | WebAssembly with WASIp3 diff --git a/src/doc/rustc/src/platform-support/armv7a-none-eabi.md b/src/doc/rustc/src/platform-support/armv7a-none-eabi.md index 05afb4f4321be..6e08bbb26e466 100644 --- a/src/doc/rustc/src/platform-support/armv7a-none-eabi.md +++ b/src/doc/rustc/src/platform-support/armv7a-none-eabi.md @@ -1,10 +1,12 @@ -# `armv7a-none-eabi` and `armv7a-none-eabihf` +# `armv7a-none-eabi` and `thumbv7a-none-eabihf` -* **Tier: 2** +* **Tier: 2** (`armv7a-none-eabi`) +* **Tier: 3** (`thumbv7a-none-eabi`) * **Library Support:** core and alloc (bare-metal, `#![no_std]`) -Bare-metal target for CPUs in the Armv7-A architecture family, supporting -dual ARM/Thumb mode, with ARM mode as the default. +Bare-metal target for CPUs in the Armv7-A architecture family, supporting dual +ARM/Thumb mode. The `armv7a-none-eabi` target uses Arm mode by default and +the `thumbv7a-none-eabihf` target uses Thumb mode by default. Note, this is for processors running in AArch32 mode. For the AArch64 mode added in Armv8-A, see [`aarch64-unknown-none`](aarch64-unknown-none.md) instead. diff --git a/src/doc/rustc/src/platform-support/armv7r-none-eabi.md b/src/doc/rustc/src/platform-support/armv7r-none-eabi.md index 7f22a29f2ee68..16755ff8c520c 100644 --- a/src/doc/rustc/src/platform-support/armv7r-none-eabi.md +++ b/src/doc/rustc/src/platform-support/armv7r-none-eabi.md @@ -1,10 +1,12 @@ # `armv7r-none-eabi` and `armv7r-none-eabihf` -* **Tier: 2** +* **Tier: 2** (`armv7r-none-eabi`) +* **Tier: 3** (`thumbv7r-none-eabi`) * **Library Support:** core and alloc (bare-metal, `#![no_std]`) -Bare-metal target for CPUs in the Armv7-R architecture family, supporting -dual ARM/Thumb mode, with ARM mode as the default. +Bare-metal target for CPUs in the Armv7-R architecture family, supporting dual +ARM/Thumb mode. The `armv7r-none-eabi` target uses Arm mode by default and +the `thumbv7r-none-eabihf` target uses Thumb mode by default. Processors in this family include the [Arm Cortex-R4, 5, 7, and 8][cortex-r]. diff --git a/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md b/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md index 369e86dbfc7e8..ad4764122446e 100644 --- a/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md +++ b/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md @@ -1,10 +1,12 @@ -# `armv8r-none-eabihf` +# `armv8r-none-eabihf` and `thumbv8r-none-eabihf` -* **Tier: 2** +* **Tier: 2**: `armv8r-none-eabihf` +* **Tier: 3**: `thumbv8r-none-eabihf` * **Library Support:** core and alloc (bare-metal, `#![no_std]`) -Bare-metal target for CPUs in the Armv8-R architecture family, supporting -dual ARM/Thumb mode, with ARM mode as the default. +Bare-metal target for CPUs in the Armv8-R architecture family, supporting dual +ARM/Thumb mode. The `armv8r-none-eabi` target uses Arm mode by default and +the `thumbv8r-none-eabihf` target uses Thumb mode by default. Processors in this family include the Arm [Cortex-R52][cortex-r52] and [Cortex-R52+][cortex-r52-plus]. diff --git a/tests/assembly-llvm/targets/targets-elf.rs b/tests/assembly-llvm/targets/targets-elf.rs index 0eced9df3c46d..17553fc8f4e40 100644 --- a/tests/assembly-llvm/targets/targets-elf.rs +++ b/tests/assembly-llvm/targets/targets-elf.rs @@ -559,6 +559,21 @@ //@ revisions: thumbv5te_none_eabi //@ [thumbv5te_none_eabi] compile-flags: --target thumbv5te-none-eabi //@ [thumbv5te_none_eabi] needs-llvm-components: arm +//@ revisions: thumbv7a_none_eabi +//@ [thumbv7a_none_eabi] compile-flags: --target thumbv7a-none-eabi +//@ [thumbv7a_none_eabi] needs-llvm-components: arm +//@ revisions: thumbv7a_none_eabihf +//@ [thumbv7a_none_eabihf] compile-flags: --target thumbv7a-none-eabihf +//@ [thumbv7a_none_eabihf] needs-llvm-components: arm +//@ revisions: thumbv7r_none_eabi +//@ [thumbv7r_none_eabi] compile-flags: --target thumbv7r-none-eabi +//@ [thumbv7r_none_eabi] needs-llvm-components: arm +//@ revisions: thumbv7r_none_eabihf +//@ [thumbv7r_none_eabihf] compile-flags: --target thumbv7r-none-eabihf +//@ [thumbv7r_none_eabihf] needs-llvm-components: arm +//@ revisions: thumbv8r_none_eabihf +//@ [thumbv8r_none_eabihf] compile-flags: --target thumbv8r-none-eabihf +//@ [thumbv8r_none_eabihf] needs-llvm-components: arm //@ revisions: thumbv6m_none_eabi //@ [thumbv6m_none_eabi] compile-flags: --target thumbv6m-none-eabi //@ [thumbv6m_none_eabi] needs-llvm-components: arm From fb05cac2aa0c5eb23a8b1603955daa9426f9ae85 Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Thu, 1 Jan 2026 17:18:48 +0000 Subject: [PATCH 06/18] Update SUMMARY.md too --- src/doc/rustc/src/SUMMARY.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/doc/rustc/src/SUMMARY.md b/src/doc/rustc/src/SUMMARY.md index 8ceeff2c9685e..5d000c900aaaf 100644 --- a/src/doc/rustc/src/SUMMARY.md +++ b/src/doc/rustc/src/SUMMARY.md @@ -56,15 +56,15 @@ - [arm-none-eabi](platform-support/arm-none-eabi.md) - [{arm,thumb}v4t-none-eabi](platform-support/armv4t-none-eabi.md) - [{arm,thumb}v5te-none-eabi](platform-support/armv5te-none-eabi.md) - - [armv7a-none-eabi{,hf}](platform-support/armv7a-none-eabi.md) - - [armv7r-none-eabi{,hf}](platform-support/armv7r-none-eabi.md) - - [armebv7r-none-eabi{,hf}](platform-support/armebv7r-none-eabi.md) - - [armv8r-none-eabihf](platform-support/armv8r-none-eabihf.md) + - [{arm,thumb}v7a-none-eabi{,hf}](platform-support/armv7a-none-eabi.md) + - [{arm,thumb}v7r-none-eabi{,hf}](platform-support/armv7r-none-eabi.md) + - [{arm,thumb}v8r-none-eabihf](platform-support/armv8r-none-eabihf.md) - [thumbv6m-none-eabi](./platform-support/thumbv6m-none-eabi.md) - [thumbv7em-none-eabi\*](./platform-support/thumbv7em-none-eabi.md) - [thumbv7m-none-eabi](./platform-support/thumbv7m-none-eabi.md) - [thumbv8m.base-none-eabi](./platform-support/thumbv8m.base-none-eabi.md) - [thumbv8m.main-none-eabi\*](./platform-support/thumbv8m.main-none-eabi.md) + - [armebv7r-none-eabi{,hf}](platform-support/armebv7r-none-eabi.md) - [arm\*-unknown-linux-\*](./platform-support/arm-linux.md) - [armeb-unknown-linux-gnueabi](platform-support/armeb-unknown-linux-gnueabi.md) - [armv5te-unknown-linux-gnueabi](platform-support/armv5te-unknown-linux-gnueabi.md) From 0a2bb4b45b5b5344895de12759081b81271dd3b3 Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Thu, 22 Jan 2026 20:48:04 +0000 Subject: [PATCH 07/18] Ensure armv7a-none-eabi.md mentions all four targets --- .../rustc/src/platform-support/armv7a-none-eabi.md | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/doc/rustc/src/platform-support/armv7a-none-eabi.md b/src/doc/rustc/src/platform-support/armv7a-none-eabi.md index 6e08bbb26e466..555f69e81a02f 100644 --- a/src/doc/rustc/src/platform-support/armv7a-none-eabi.md +++ b/src/doc/rustc/src/platform-support/armv7a-none-eabi.md @@ -1,12 +1,14 @@ -# `armv7a-none-eabi` and `thumbv7a-none-eabihf` +# `armv7a-none-eabi*` and `thumbv7a-none-eabi*` -* **Tier: 2** (`armv7a-none-eabi`) -* **Tier: 3** (`thumbv7a-none-eabi`) +* **Tier: 2** (`armv7a-none-eabi` and `armv7a-none-eabihf`) +* **Tier: 3** (`thumbv7a-none-eabi` and `thumbv7a-none-eabihf`) * **Library Support:** core and alloc (bare-metal, `#![no_std]`) Bare-metal target for CPUs in the Armv7-A architecture family, supporting dual -ARM/Thumb mode. The `armv7a-none-eabi` target uses Arm mode by default and -the `thumbv7a-none-eabihf` target uses Thumb mode by default. +ARM/Thumb mode. The `armv7a-none-eabi*` targets use Arm mode by default and the +`thumbv7a-none-eabi` targets use Thumb mode by default. The `-eabi` targets use +a soft-float ABI and do not require an FPU, while the `-eabihf` targets use a +hard-float ABI and do require an FPU. Note, this is for processors running in AArch32 mode. For the AArch64 mode added in Armv8-A, see [`aarch64-unknown-none`](aarch64-unknown-none.md) instead. From 19d1be5de6d57d56c95c5ee77e493ee894bfbe69 Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Thu, 22 Jan 2026 20:48:11 +0000 Subject: [PATCH 08/18] Ensure armv7r-none-eabi.md mentions all four targets --- .../src/platform-support/armv7r-none-eabi.md | 22 ++++++++++--------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/src/doc/rustc/src/platform-support/armv7r-none-eabi.md b/src/doc/rustc/src/platform-support/armv7r-none-eabi.md index 16755ff8c520c..20fd55c6abd68 100644 --- a/src/doc/rustc/src/platform-support/armv7r-none-eabi.md +++ b/src/doc/rustc/src/platform-support/armv7r-none-eabi.md @@ -1,12 +1,14 @@ -# `armv7r-none-eabi` and `armv7r-none-eabihf` +# `armv7r-none-eabi*` and `thumbv7r-none-eabi*` -* **Tier: 2** (`armv7r-none-eabi`) -* **Tier: 3** (`thumbv7r-none-eabi`) +* **Tier: 2** (`armv7r-none-eabi` and `armv7r-none-eabihf`) +* **Tier: 3** (`thumbv7r-none-eabi` and `thumbv7r-none-eabihf`) * **Library Support:** core and alloc (bare-metal, `#![no_std]`) Bare-metal target for CPUs in the Armv7-R architecture family, supporting dual -ARM/Thumb mode. The `armv7r-none-eabi` target uses Arm mode by default and -the `thumbv7r-none-eabihf` target uses Thumb mode by default. +ARM/Thumb mode. The `armv7r-none-eabi*` targets use Arm mode by default and the +`thumbv7r-none-eabi*` targets use Thumb mode by default. The `-eabi` targets use +a soft-float ABI and do not require an FPU, while the `-eabihf` targets use a +hard-float ABI and do require an FPU. Processors in this family include the [Arm Cortex-R4, 5, 7, and 8][cortex-r]. @@ -27,11 +29,11 @@ See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all ## Requirements -When using the hardfloat targets, the minimum floating-point features assumed -are those of the `vfpv3-d16`, which includes single- and double-precision, with -16 double-precision registers. This floating-point unit appears in Cortex-R4F -and Cortex-R5F processors. See [VFP in the Cortex-R processors][vfp] -for more details on the possible FPU variants. +When using the hardfloat (`-eabibf`) targets, the minimum floating-point +features assumed are those of the `vfpv3-d16`, which includes single- and +double-precision, with 16 double-precision registers. This floating-point unit +appears in Cortex-R4F and Cortex-R5F processors. See [VFP in the Cortex-R +processors][vfp] for more details on the possible FPU variants. If your processor supports a different set of floating-point features than the default expectations of `vfpv3-d16`, then these should also be enabled or From fa526c47ccdc2bcc184d49bc7548a57434b0e7b9 Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Thu, 22 Jan 2026 20:50:09 +0000 Subject: [PATCH 09/18] Update armv8r-none-eabi.md - note both targets are hardfloat --- src/doc/rustc/src/platform-support/armv8r-none-eabihf.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md b/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md index ad4764122446e..85abac3d7eb89 100644 --- a/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md +++ b/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md @@ -5,8 +5,9 @@ * **Library Support:** core and alloc (bare-metal, `#![no_std]`) Bare-metal target for CPUs in the Armv8-R architecture family, supporting dual -ARM/Thumb mode. The `armv8r-none-eabi` target uses Arm mode by default and -the `thumbv8r-none-eabihf` target uses Thumb mode by default. +ARM/Thumb mode. The `armv8r-none-eabihf` target uses Arm mode by default and +the `thumbv8r-none-eabihf` target uses Thumb mode by default. Both targets +use a hard-float ABI and require an FPU. Processors in this family include the Arm [Cortex-R52][cortex-r52] and [Cortex-R52+][cortex-r52-plus]. From c609cce8cf6c6a5a1b6e081a671c7ba9f1165fdd Mon Sep 17 00:00:00 2001 From: Andreas Liljeqvist Date: Thu, 22 Jan 2026 22:18:00 +0100 Subject: [PATCH 10/18] Merge is_ascii codegen tests using revisions Combine the x86_64 and loongarch64 is_ascii tests into a single file using compiletest revisions. Both now test assembly output: - X86_64: Verifies no broken kshiftrd/kshiftrq instructions (AVX-512 fix) - LA64: Verifies vmskltz.b instruction is used (auto-vectorization) --- tests/assembly-llvm/slice-is-ascii-avx512.rs | 18 ----------- tests/assembly-llvm/slice-is-ascii.rs | 32 ++++++++++++++++++++ tests/codegen-llvm/slice-is-ascii.rs | 19 ------------ 3 files changed, 32 insertions(+), 37 deletions(-) delete mode 100644 tests/assembly-llvm/slice-is-ascii-avx512.rs create mode 100644 tests/assembly-llvm/slice-is-ascii.rs delete mode 100644 tests/codegen-llvm/slice-is-ascii.rs diff --git a/tests/assembly-llvm/slice-is-ascii-avx512.rs b/tests/assembly-llvm/slice-is-ascii-avx512.rs deleted file mode 100644 index d3a441fec96cb..0000000000000 --- a/tests/assembly-llvm/slice-is-ascii-avx512.rs +++ /dev/null @@ -1,18 +0,0 @@ -//@ only-x86_64 -//@ compile-flags: -C opt-level=3 -C target-cpu=znver4 -//@ compile-flags: -C llvm-args=-x86-asm-syntax=intel -//@ assembly-output: emit-asm -#![crate_type = "lib"] - -// Verify is_ascii uses pmovmskb/vpmovmskb instead of kshiftrd with AVX-512. -// The fix uses explicit SSE2 intrinsics to avoid LLVM's broken auto-vectorization. -// -// See: https://github.com/rust-lang/rust/issues/129293 - -// CHECK-LABEL: test_is_ascii -#[no_mangle] -pub fn test_is_ascii(s: &[u8]) -> bool { - // CHECK-NOT: kshiftrd - // CHECK-NOT: kshiftrq - s.is_ascii() -} diff --git a/tests/assembly-llvm/slice-is-ascii.rs b/tests/assembly-llvm/slice-is-ascii.rs new file mode 100644 index 0000000000000..d01b321bf460a --- /dev/null +++ b/tests/assembly-llvm/slice-is-ascii.rs @@ -0,0 +1,32 @@ +//@ revisions: X86_64 LA64 +//@ assembly-output: emit-asm +//@ compile-flags: -C opt-level=3 +// +//@ [X86_64] only-x86_64 +//@ [X86_64] compile-flags: -C target-cpu=znver4 +//@ [X86_64] compile-flags: -C llvm-args=-x86-asm-syntax=intel +// +//@ [LA64] only-loongarch64 + +#![crate_type = "lib"] + +/// Verify `is_ascii` generates efficient code on different architectures: +/// +/// - x86_64: Must NOT use `kshiftrd`/`kshiftrq` (broken AVX-512 auto-vectorization). +/// The fix uses explicit SSE2 intrinsics (`pmovmskb`/`vpmovmskb`). +/// See: https://github.com/llvm/llvm-project/issues/176906 +/// +/// - loongarch64: Should use `vmskltz.b` instruction for the fast-path. +/// This architecture still relies on LLVM auto-vectorization. + +// X86_64-LABEL: test_is_ascii +// X86_64-NOT: kshiftrd +// X86_64-NOT: kshiftrq + +// LA64-LABEL: test_is_ascii +// LA64: vmskltz.b + +#[no_mangle] +pub fn test_is_ascii(s: &[u8]) -> bool { + s.is_ascii() +} diff --git a/tests/codegen-llvm/slice-is-ascii.rs b/tests/codegen-llvm/slice-is-ascii.rs deleted file mode 100644 index 1f41b69e43966..0000000000000 --- a/tests/codegen-llvm/slice-is-ascii.rs +++ /dev/null @@ -1,19 +0,0 @@ -//@ only-loongarch64 -//@ compile-flags: -C opt-level=3 -#![crate_type = "lib"] - -/// Check that the fast-path of `is_ascii` uses a `vmskltz.b` instruction. -/// Platforms lacking an equivalent instruction use other techniques for -/// optimizing `is_ascii`. -/// -/// Note: x86_64 uses explicit SSE2 intrinsics instead of relying on -/// auto-vectorization. See `slice-is-ascii-avx512.rs`. -// CHECK-LABEL: @is_ascii_autovectorized -#[no_mangle] -pub fn is_ascii_autovectorized(s: &[u8]) -> bool { - // CHECK: load <32 x i8> - // CHECK-NEXT: icmp slt <32 x i8> - // CHECK-NEXT: bitcast <32 x i1> - // CHECK-NEXT: icmp eq i32 - s.is_ascii() -} From 890c0fd4e8a3cbd49b761db2432114b147ae3487 Mon Sep 17 00:00:00 2001 From: Andreas Liljeqvist Date: Thu, 22 Jan 2026 22:41:57 +0100 Subject: [PATCH 11/18] Make is_ascii_sse2 a safe function Remove the `#[target_feature(enable = "sse2")]` attribute and make the function safe to call. The SSE2 requirement is already enforced by the `#[cfg(target_feature = "sse2")]` predicate. Individual unsafe blocks are used for intrinsic calls with appropriate SAFETY comments. Also adds FIXME reference to llvm#176906 for tracking when this workaround can be removed. --- library/core/src/slice/ascii.rs | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/library/core/src/slice/ascii.rs b/library/core/src/slice/ascii.rs index 25b8a10af3555..459c826f40646 100644 --- a/library/core/src/slice/ascii.rs +++ b/library/core/src/slice/ascii.rs @@ -467,11 +467,9 @@ const CHUNK_SIZE: usize = 32; /// SSE2 implementation using `_mm_movemask_epi8` (compiles to `pmovmskb`) to /// avoid LLVM's broken AVX-512 auto-vectorization of counting loops. /// -/// # Safety -/// Requires SSE2 support (guaranteed on x86_64). +/// FIXME(llvm#176906): Remove this workaround once LLVM generates efficient code. #[cfg(all(target_arch = "x86_64", target_feature = "sse2"))] -#[target_feature(enable = "sse2")] -unsafe fn is_ascii_sse2(bytes: &[u8]) -> bool { +fn is_ascii_sse2(bytes: &[u8]) -> bool { use crate::arch::x86_64::{__m128i, _mm_loadu_si128, _mm_movemask_epi8, _mm_or_si128}; let mut i = 0; @@ -487,12 +485,14 @@ unsafe fn is_ascii_sse2(bytes: &[u8]) -> bool { // SAFETY: Same as above - ptr.add(16) is within the valid 32-byte range. let chunk2 = unsafe { _mm_loadu_si128(ptr.add(16) as *const __m128i) }; - // OR them together - if any byte has the high bit set, the result will too - let combined = _mm_or_si128(chunk1, chunk2); + // OR them together - if any byte has the high bit set, the result will too. + // SAFETY: SSE2 is guaranteed by the cfg predicate. + let combined = unsafe { _mm_or_si128(chunk1, chunk2) }; // Create a mask from the MSBs of each byte. // If any byte is >= 128, its MSB is 1, so the mask will be non-zero. - let mask = _mm_movemask_epi8(combined); + // SAFETY: SSE2 is guaranteed by the cfg predicate. + let mask = unsafe { _mm_movemask_epi8(combined) }; if mask != 0 { return false; @@ -541,8 +541,7 @@ const fn is_ascii(bytes: &[u8]) -> bool { return remainder.iter().all(|b| b.is_ascii()); } - // SAFETY: SSE2 is guaranteed available on x86_64 - unsafe { is_ascii_sse2(bytes) } + is_ascii_sse2(bytes) } ) } From ff9c5cfd2813aebdfa97057d892b81807d4f2ad8 Mon Sep 17 00:00:00 2001 From: paradoxicalguy Date: Thu, 22 Jan 2026 22:37:29 +0000 Subject: [PATCH 12/18] Enable reproducible binary builds with debuginfo on Linux --- tests/run-make/reproducible-build/rmake.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/run-make/reproducible-build/rmake.rs b/tests/run-make/reproducible-build/rmake.rs index 93fc30de07d7e..b4796c806a615 100644 --- a/tests/run-make/reproducible-build/rmake.rs +++ b/tests/run-make/reproducible-build/rmake.rs @@ -205,7 +205,7 @@ fn diff_dir_test(crate_type: CrateType, remap_type: RemapType) { // See https://github.com/rust-lang/rust/issues/89911 // FIXME(#129117): Windows rlib + `-Cdebuginfo=2` + `-Z remap-cwd-prefix=.` seems // to be unreproducible. - if !matches!(crate_type, CrateType::Bin) && !is_windows() { + if !is_windows() { compiler1.arg("-Cdebuginfo=2"); compiler2.arg("-Cdebuginfo=2"); } From 081c4c6abbdefdaab43d42875305db2fdcb359e9 Mon Sep 17 00:00:00 2001 From: bendn Date: Thu, 22 Jan 2026 21:08:11 +0700 Subject: [PATCH 13/18] reenable tests --- library/coretests/tests/bool.rs | 12 ++++++++++-- library/coretests/tests/lib.rs | 1 + 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/library/coretests/tests/bool.rs b/library/coretests/tests/bool.rs index eb5f0f50663e1..3f4588f525783 100644 --- a/library/coretests/tests/bool.rs +++ b/library/coretests/tests/bool.rs @@ -89,7 +89,6 @@ fn test_bool_to_option() { assert_eq!(false.then(|| 0), None); assert_eq!(true.then(|| 0), Some(0)); - /* FIXME(#110395) const fn zero() -> i32 { 0 } @@ -103,7 +102,6 @@ fn test_bool_to_option() { assert_eq!(B, Some(0)); assert_eq!(C, None); assert_eq!(D, Some(0)); - */ } #[test] @@ -112,4 +110,14 @@ fn test_bool_to_result() { assert_eq!(true.ok_or(0), Ok(())); assert_eq!(false.ok_or_else(|| 0), Err(0)); assert_eq!(true.ok_or_else(|| 0), Ok(())); + + const A: Result<(), i32> = false.ok_or(0); + const B: Result<(), i32> = true.ok_or(0); + const C: Result<(), i32> = false.ok_or_else(zero); + const D: Result<(), i32> = true.ok_or_else(zero); + + assert_eq!(A, Err(0)); + assert_eq!(B, Ok(())); + assert_eq!(C, Err(0)); + assert_eq!(D, Ok(())); } diff --git a/library/coretests/tests/lib.rs b/library/coretests/tests/lib.rs index 8c91567fc94a0..8cca714b73933 100644 --- a/library/coretests/tests/lib.rs +++ b/library/coretests/tests/lib.rs @@ -17,6 +17,7 @@ #![feature(clamp_magnitude)] #![feature(clone_to_uninit)] #![feature(const_array)] +#![feature(const_bool)] #![feature(const_cell_traits)] #![feature(const_clone)] #![feature(const_cmp)] From 1e8ffd9ce58ae197e77d819e2be40f6ce0aceef7 Mon Sep 17 00:00:00 2001 From: abhinav srivastav <136164196+paradoxicalguy@users.noreply.github.com> Date: Fri, 23 Jan 2026 13:10:21 +0530 Subject: [PATCH 14/18] Removed comment on reproducibility issue #89911 Removed comment about reproducibility failures with crate type `bin` and `-Cdebuginfo=2` on non windows machines issue #89911 --- tests/run-make/reproducible-build/rmake.rs | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tests/run-make/reproducible-build/rmake.rs b/tests/run-make/reproducible-build/rmake.rs index b4796c806a615..993c2c8092a6b 100644 --- a/tests/run-make/reproducible-build/rmake.rs +++ b/tests/run-make/reproducible-build/rmake.rs @@ -199,10 +199,6 @@ fn diff_dir_test(crate_type: CrateType, remap_type: RemapType) { .arg(format!("--remap-path-prefix={}=/b", base_dir.join("test").display())); } RemapType::Cwd { is_empty } => { - // FIXME(Oneirical): Building with crate type set to `bin` AND having -Cdebuginfo=2 - // (or `-g`, the shorthand form) enabled will cause reproducibility failures - // for multiple platforms. - // See https://github.com/rust-lang/rust/issues/89911 // FIXME(#129117): Windows rlib + `-Cdebuginfo=2` + `-Z remap-cwd-prefix=.` seems // to be unreproducible. if !is_windows() { From 207dcbbe7c693dec30eae387f28ad88d88fe7265 Mon Sep 17 00:00:00 2001 From: bendn Date: Thu, 22 Jan 2026 19:29:55 +0700 Subject: [PATCH 15/18] constify boolean methods --- library/core/src/bool.rs | 17 +++++++++++++---- library/coretests/tests/bool.rs | 8 ++++---- 2 files changed, 17 insertions(+), 8 deletions(-) diff --git a/library/core/src/bool.rs b/library/core/src/bool.rs index 99268d6182f6c..9b9d2f02550bd 100644 --- a/library/core/src/bool.rs +++ b/library/core/src/bool.rs @@ -1,5 +1,7 @@ //! impl bool {} +use crate::marker::Destruct; + impl bool { /// Returns `Some(t)` if the `bool` is [`true`](../std/keyword.true.html), /// or `None` otherwise. @@ -29,8 +31,9 @@ impl bool { /// assert_eq!(a, 2); /// ``` #[stable(feature = "bool_to_option", since = "1.62.0")] + #[rustc_const_unstable(feature = "const_bool", issue = "151531")] #[inline] - pub fn then_some(self, t: T) -> Option { + pub const fn then_some(self, t: T) -> Option { if self { Some(t) } else { None } } @@ -57,8 +60,9 @@ impl bool { #[doc(alias = "then_with")] #[stable(feature = "lazy_bool_to_option", since = "1.50.0")] #[rustc_diagnostic_item = "bool_then"] + #[rustc_const_unstable(feature = "const_bool", issue = "151531")] #[inline] - pub fn then T>(self, f: F) -> Option { + pub const fn then T + [const] Destruct>(self, f: F) -> Option { if self { Some(f()) } else { None } } @@ -94,8 +98,9 @@ impl bool { /// assert_eq!(a, 2); /// ``` #[unstable(feature = "bool_to_result", issue = "142748")] + #[rustc_const_unstable(feature = "const_bool", issue = "151531")] #[inline] - pub fn ok_or(self, err: E) -> Result<(), E> { + pub const fn ok_or(self, err: E) -> Result<(), E> { if self { Ok(()) } else { Err(err) } } @@ -124,8 +129,12 @@ impl bool { /// assert_eq!(a, 1); /// ``` #[unstable(feature = "bool_to_result", issue = "142748")] + #[rustc_const_unstable(feature = "const_bool", issue = "151531")] #[inline] - pub fn ok_or_else E>(self, f: F) -> Result<(), E> { + pub const fn ok_or_else E + [const] Destruct>( + self, + f: F, + ) -> Result<(), E> { if self { Ok(()) } else { Err(f()) } } } diff --git a/library/coretests/tests/bool.rs b/library/coretests/tests/bool.rs index 3f4588f525783..802e43045b6e6 100644 --- a/library/coretests/tests/bool.rs +++ b/library/coretests/tests/bool.rs @@ -82,6 +82,10 @@ pub fn test_bool_not() { } } +const fn zero() -> i32 { + 0 +} + #[test] fn test_bool_to_option() { assert_eq!(false.then_some(0), None); @@ -89,10 +93,6 @@ fn test_bool_to_option() { assert_eq!(false.then(|| 0), None); assert_eq!(true.then(|| 0), Some(0)); - const fn zero() -> i32 { - 0 - } - const A: Option = false.then_some(0); const B: Option = true.then_some(0); const C: Option = false.then(zero); From 78afe876f428daa694bf90aeb6461a0a59d568ef Mon Sep 17 00:00:00 2001 From: ThanhNguyxn Date: Fri, 23 Jan 2026 10:37:55 +0700 Subject: [PATCH 16/18] Add 'Skip to main content' link for keyboard navigation in rustdoc Implements WCAG 2.4.1 (Level A) - Bypass Blocks accessibility feature. Changes: - Add skip-main-content link in page.html with tabindex=-1 on main-content - Add CSS styling per reviewer feedback (outline border, themed colors) - Add GOML test for skip navigation functionality Fixes #151420 --- src/librustdoc/html/static/css/rustdoc.css | 19 +++++++++++++++++++ src/librustdoc/html/templates/page.html | 3 ++- tests/rustdoc-gui/skip-navigation.goml | 19 +++++++++++++++++++ 3 files changed, 40 insertions(+), 1 deletion(-) create mode 100644 tests/rustdoc-gui/skip-navigation.goml diff --git a/src/librustdoc/html/static/css/rustdoc.css b/src/librustdoc/html/static/css/rustdoc.css index 486ca9b22539c..6c34d31cc918c 100644 --- a/src/librustdoc/html/static/css/rustdoc.css +++ b/src/librustdoc/html/static/css/rustdoc.css @@ -210,6 +210,24 @@ body { color: var(--main-color); } +/* Skip navigation link for keyboard users (WCAG 2.4.1) */ +.skip-main-content { + position: absolute; + left: 0; + top: -100%; + z-index: 1000; + padding: 0.5rem 1rem; + background-color: var(--main-background-color); + color: var(--main-color); + text-decoration: none; + font-weight: 500; + border-bottom-right-radius: 4px; + outline: 2px solid var(--search-input-focused-border-color); +} +.skip-main-content:focus { + top: 0; +} + h1 { font-size: 1.5rem; /* 24px */ } @@ -1114,6 +1132,7 @@ pre, .rustdoc.src .example-wrap, .example-wrap .src-line-numbers { #main-content { position: relative; + outline: none; } .docblock table { diff --git a/src/librustdoc/html/templates/page.html b/src/librustdoc/html/templates/page.html index 1f8ec9f30c53c..427e7b4071a1e 100644 --- a/src/librustdoc/html/templates/page.html +++ b/src/librustdoc/html/templates/page.html @@ -66,6 +66,7 @@ {{ layout.external_html.in_header|safe }} {# #} {# #} + Skip to main content {# #}