diff --git a/include/circt/Dialect/FIRRTL/AnnotationDetails.h b/include/circt/Dialect/FIRRTL/AnnotationDetails.h index 4d6282e3468a..98415d3b100c 100644 --- a/include/circt/Dialect/FIRRTL/AnnotationDetails.h +++ b/include/circt/Dialect/FIRRTL/AnnotationDetails.h @@ -161,12 +161,6 @@ constexpr const char *loadMemoryFromFileAnnoClass = constexpr const char *loadMemoryFromFileInlineAnnoClass = "firrtl.annotations.MemoryFileInlineAnnotation"; -// WiringTransform Annotations -constexpr const char *wiringSinkAnnoClass = - "firrtl.passes.wiring.SinkAnnotation"; -constexpr const char *wiringSourceAnnoClass = - "firrtl.passes.wiring.SourceAnnotation"; - // Attribute annotations. constexpr const char *attributeAnnoClass = "firrtl.AttributeAnnotation"; diff --git a/include/circt/Dialect/FIRRTL/FIRRTLAnnotationHelper.h b/include/circt/Dialect/FIRRTL/FIRRTLAnnotationHelper.h index ac59692226f2..660ad010f3a9 100644 --- a/include/circt/Dialect/FIRRTL/FIRRTLAnnotationHelper.h +++ b/include/circt/Dialect/FIRRTL/FIRRTLAnnotationHelper.h @@ -279,16 +279,6 @@ struct WiringProblem { RefTypeUsage refTypeUsage; }; -/// A representation of a legacy Wiring problem consisting of a signal source -/// that should be connected to one or many sinks. -struct LegacyWiringProblem { - /// A source to wire from. - Value source; - - /// Sink(s) to wire to. - SmallVector sinks; -}; - /// A store of pending modifications to a FIRRTL module associated with solving /// one or more WiringProblems. struct ModuleModifications { @@ -356,7 +346,6 @@ struct ApplyState { bool noRefTypePorts; DenseSet wiringProblemInstRefs; - DenseMap legacyWiringProblems; SmallVector wiringProblems; hw::InnerSymbolNamespace &getNamespace(FModuleLike module) { diff --git a/lib/Dialect/FIRRTL/Transforms/CMakeLists.txt b/lib/Dialect/FIRRTL/Transforms/CMakeLists.txt index 24202fbc0e5f..b40a20d6d23f 100755 --- a/lib/Dialect/FIRRTL/Transforms/CMakeLists.txt +++ b/lib/Dialect/FIRRTL/Transforms/CMakeLists.txt @@ -23,7 +23,6 @@ add_circt_dialect_library(CIRCTFIRRTLTransforms InferWidths.cpp InjectDUTHierarchy.cpp InnerSymbolDCE.cpp - LegacyWiring.cpp LinkCircuits.cpp Lint.cpp LayerMerge.cpp diff --git a/lib/Dialect/FIRRTL/Transforms/LegacyWiring.cpp b/lib/Dialect/FIRRTL/Transforms/LegacyWiring.cpp deleted file mode 100644 index d83391fccadb..000000000000 --- a/lib/Dialect/FIRRTL/Transforms/LegacyWiring.cpp +++ /dev/null @@ -1,103 +0,0 @@ -//===- LegacyWiring- legacy Wiring annotation resolver --------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file defines the legacy Wiring annotation resolver. -// -//===----------------------------------------------------------------------===// - -#include "circt/Dialect/FIRRTL/AnnotationDetails.h" -#include "circt/Dialect/FIRRTL/FIRRTLAnnotationHelper.h" -#include "circt/Dialect/FIRRTL/FIRRTLAnnotations.h" -#include "circt/Dialect/FIRRTL/FIRRTLUtils.h" - -using namespace circt; -using namespace firrtl; - -/// Consume SourceAnnotation and SinkAnnotation, storing into state -LogicalResult circt::firrtl::applyWiring(const AnnoPathValue &target, - DictionaryAttr anno, - ApplyState &state) { - auto clazz = anno.getAs("class").getValue(); - auto *context = anno.getContext(); - ImplicitLocOpBuilder builder(target.ref.getOp()->getLoc(), context); - - // Convert target to Value - Value targetValue; - if (auto portTarget = dyn_cast(target.ref)) { - auto portNum = portTarget.getImpl().getPortNo(); - if (auto module = dyn_cast(portTarget.getOp())) { - if (clazz == wiringSourceAnnoClass) { - builder.setInsertionPointToStart(module.getBodyBlock()); - } else if (clazz == wiringSinkAnnoClass) { - builder.setInsertionPointToEnd(module.getBodyBlock()); - } - targetValue = getValueByFieldID(builder, module.getArgument(portNum), - target.fieldIdx); - } else if (auto ext = dyn_cast(portTarget.getOp())) { - InstanceOp inst; - if (target.instances.empty()) { - auto paths = state.instancePathCache.getAbsolutePaths(ext); - if (paths.size() > 1) { - mlir::emitError(state.circuit.getLoc()) - << "cannot resolve a unique instance path from the " - "external module target " - << target.ref; - return failure(); - } - inst = cast(paths[0].leaf()); - } else { - inst = cast(target.instances.back()); - } - state.wiringProblemInstRefs.insert(inst); - builder.setInsertionPointAfter(inst); - targetValue = - getValueByFieldID(builder, inst->getResult(portNum), target.fieldIdx); - } else { - return mlir::emitError(state.circuit.getLoc()) - << "Annotation has invalid target: " << anno; - } - } else if (auto opResult = dyn_cast(target.ref)) { - if (target.isOpOfType()) { - auto *targetBase = opResult.getOp(); - builder.setInsertionPointAfter(targetBase); - targetValue = - getValueByFieldID(builder, targetBase->getResult(0), target.fieldIdx); - } else { - return mlir::emitError(state.circuit.getLoc()) - << "Annotation targets non-wireable operation: " << anno; - } - } else { - return mlir::emitError(state.circuit.getLoc()) - << "Annotation has invalid target: " << anno; - } - - // Get pin field - auto pin = anno.getAs("pin"); - if (!pin) { - return mlir::emitError(state.circuit.getLoc()) - << "Annotation does not have an associated pin name: " << anno; - } - - // Handle difference between sinks and sources - if (clazz == wiringSourceAnnoClass) { - if (state.legacyWiringProblems.find(pin) != - state.legacyWiringProblems.end()) { - // Check if existing problem can be updated - if (state.legacyWiringProblems[pin].source) { - return mlir::emitError(state.circuit.getLoc()) - << "More than one " << wiringSourceAnnoClass - << " defined for pin " << pin; - } - } - state.legacyWiringProblems[pin].source = targetValue; - } else if (clazz == wiringSinkAnnoClass) { - state.legacyWiringProblems[pin].sinks.push_back(targetValue); - } - - return success(); -} diff --git a/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp b/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp index 78095dee4b06..507ecdd0c934 100644 --- a/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp +++ b/lib/Dialect/FIRRTL/Transforms/LowerAnnotations.cpp @@ -672,8 +672,6 @@ static llvm::StringMap annotationRecords{{ {loadMemoryFromFileAnnoClass, {stdResolve, applyLoadMemoryAnno}}, {loadMemoryFromFileInlineAnnoClass, {stdResolve, applyLoadMemoryAnno}}, - {wiringSinkAnnoClass, {stdResolve, applyWiring}}, - {wiringSourceAnnoClass, {stdResolve, applyWiring}}, {attributeAnnoClass, {stdResolve, applyAttributeAnnotation}}}}; LogicalResult @@ -713,7 +711,6 @@ struct LowerAnnotationsPass void runOnOperation() override; LogicalResult applyAnnotation(DictionaryAttr anno, ApplyState &state); - LogicalResult legacyToWiringProblems(ApplyState &state); LogicalResult solveWiringProblems(ApplyState &state); SmallVector worklistAttrs; @@ -758,26 +755,6 @@ LogicalResult LowerAnnotationsPass::applyAnnotation(DictionaryAttr anno, return success(); } -/// Convert consumed SourceAnnotation and SinkAnnotation into WiringProblems, -/// using the pin attribute as newNameHint -LogicalResult LowerAnnotationsPass::legacyToWiringProblems(ApplyState &state) { - for (const auto &[name, problem] : state.legacyWiringProblems) { - if (!problem.source) - return mlir::emitError(state.circuit.getLoc()) - << "Unable to resolve source for pin: " << name; - - if (problem.sinks.empty()) - return mlir::emitError(state.circuit.getLoc()) - << "Unable to resolve sink(s) for pin: " << name; - - for (const auto &sink : problem.sinks) { - state.wiringProblems.push_back( - {problem.source, sink, {}, WiringProblem::RefTypeUsage::Never}); - } - } - return success(); -} - /// Modify the circuit to solve and apply all Wiring Problems in the circuit. A /// Wiring Problem is a mapping from a source to a sink that can be connected /// via a base Type or RefType as requested. This uses a two-step approach. @@ -1229,9 +1206,6 @@ void LowerAnnotationsPass::runOnOperation() { ++numFailures; } - if (failed(legacyToWiringProblems(state))) - ++numFailures; - if (failed(solveWiringProblems(state))) ++numFailures; diff --git a/test/Dialect/FIRRTL/legacy-wiring-errors.mlir b/test/Dialect/FIRRTL/legacy-wiring-errors.mlir deleted file mode 100644 index bcd766a3d319..000000000000 --- a/test/Dialect/FIRRTL/legacy-wiring-errors.mlir +++ /dev/null @@ -1,123 +0,0 @@ -// RUN: circt-opt --pass-pipeline='builtin.module(firrtl.circuit(firrtl-lower-annotations))' -split-input-file %s -verify-diagnostics - -// Every Wiring pin must have exactly one defined source -// -// expected-error @+1 {{Unable to resolve source for pin: "foo_out"}} -firrtl.circuit "Foo" attributes { - rawAnnotations = [ - { - class = "firrtl.passes.wiring.SinkAnnotation", - target = "Foo.Foo.out", - pin = "foo_out" - }]} { - firrtl.module @Foo(out %out: !firrtl.uint<1>) { - firrtl.skip - } -} - -// ----- - -// Every Wiring pin must have at least one defined sink -// -// expected-error @+1 {{Unable to resolve sink(s) for pin: "foo_in"}} -firrtl.circuit "Foo" attributes { - rawAnnotations = [ - { - class = "firrtl.passes.wiring.SourceAnnotation", - target = "Foo.Foo.in", - pin = "foo_in" - }]} { - firrtl.module @Foo(in %in: !firrtl.uint<1>) { - firrtl.skip - } -} - -// ----- - -// Multiple SourceAnnotations for the same pin are forbidden -// -// expected-error @+2 {{Unable to apply annotation: {class = "firrtl.passes.wiring.SourceAnnotation", pin = "foo_out", target = "Foo.Foo.b"}}} -// expected-error @+1 {{More than one firrtl.passes.wiring.SourceAnnotation defined for pin "foo_out"}} -firrtl.circuit "Foo" attributes { - rawAnnotations = [ - { - class = "firrtl.passes.wiring.SinkAnnotation", - target = "Foo.Foo.out", - pin = "foo_out" - }, - { - class = "firrtl.passes.wiring.SourceAnnotation", - target = "Foo.Foo.a", - pin = "foo_out" - }, - { - class = "firrtl.passes.wiring.SourceAnnotation", - target = "Foo.Foo.b", - pin = "foo_out" - }]} { - firrtl.module @Foo(in %a: !firrtl.uint<1>, in %b: !firrtl.uint<1>, out %out: !firrtl.uint<1>) { - firrtl.skip - } -} - -// ----- -// Error if attempt to wire incompatible types. - -firrtl.circuit "Foo" attributes { - rawAnnotations = [ - { - class = "firrtl.passes.wiring.SourceAnnotation", - target = "~Foo|Bar>y", - pin = "xyz" - }, - { - class = "firrtl.passes.wiring.SinkAnnotation", - target = "~Foo|Foo>x", - pin = "xyz" - } - ]} { - firrtl.module private @Bar() { - // expected-error @below {{Wiring Problem source type '!firrtl.bundle, b: uint<2>>' does not match sink type '!firrtl.uint<1>'}} - %y = firrtl.wire interesting_name : !firrtl.bundle, b: uint<2>> - %invalid_reset = firrtl.invalidvalue : !firrtl.bundle, b: uint<2>> - firrtl.matchingconnect %y, %invalid_reset : !firrtl.bundle, b: uint<2>> - } - firrtl.module @Foo() { - firrtl.instance bar interesting_name @Bar() - // expected-note @below {{The sink is here.}} - %x = firrtl.wire interesting_name : !firrtl.uint<1> - %invalid_ui1 = firrtl.invalidvalue : !firrtl.uint<1> - firrtl.matchingconnect %x, %invalid_ui1 : !firrtl.uint<1> - } -} - -// ----- - -// Error on wiring through public -firrtl.circuit "FooBar" attributes { - rawAnnotations = [ - { - class = "firrtl.passes.wiring.SinkAnnotation", - target = "FooBar.Foo.out", - pin = "foo_out" - }, - { - class = "firrtl.passes.wiring.SourceAnnotation", - target = "FooBar.FooBar.io.in", - pin = "foo_out" - }]} { - // expected-note @below {{sink here}} - firrtl.module private @Foo(out %out: !firrtl.uint<1>) { - } - // expected-error @below {{cannot wire port through this public module}} - firrtl.module public @Bar(out %out: !firrtl.uint<1>) { - %foo_out = firrtl.instance foo interesting_name @Foo(out out: !firrtl.uint<1>) - firrtl.matchingconnect %out, %foo_out : !firrtl.uint<1> - } - // expected-note @below {{source here}} - firrtl.module @FooBar(out %io: !firrtl.bundle, out: uint<1>>) { - %0 = firrtl.subfield %io[out] : !firrtl.bundle, out: uint<1>> - %bar_out = firrtl.instance bar interesting_name @Bar(out out: !firrtl.uint<1>) - firrtl.matchingconnect %0, %bar_out : !firrtl.uint<1> - } -} diff --git a/test/Dialect/FIRRTL/legacy-wiring.mlir b/test/Dialect/FIRRTL/legacy-wiring.mlir deleted file mode 100644 index d7f6669fa2ca..000000000000 --- a/test/Dialect/FIRRTL/legacy-wiring.mlir +++ /dev/null @@ -1,237 +0,0 @@ -// RUN: circt-opt --pass-pipeline='builtin.module(firrtl.circuit(firrtl-lower-annotations))' --split-input-file %s | FileCheck %s - -// Check added ports are real type -// CHECK-LABEL: firrtl.circuit "FooBar" -firrtl.circuit "FooBar" attributes { - rawAnnotations = [ - { - class = "firrtl.passes.wiring.SinkAnnotation", - target = "FooBar.Foo.io.out", - pin = "foo_out" - }, - { - class = "firrtl.passes.wiring.SourceAnnotation", - target = "FooBar.FooBar.io.in", - pin = "foo_out" - }]} { - // CHECK: firrtl.module private @Foo - // The real port type of the source should be bored - // CHECK-SAME: in %io_out__bore: !firrtl.uint<1> - firrtl.module private @Foo(out %io: !firrtl.bundle>) { - firrtl.skip - } - // CHECK: firrtl.module private @Bar - // The real port type of the source should be bored in the parent - // CHECK-SAME: in %foo_io_out__bore: !firrtl.uint<1> - firrtl.module private @Bar(out %io: !firrtl.bundle>) { - %0 = firrtl.subfield %io[out] : !firrtl.bundle> - // CHECK: firrtl.instance foo - // CHECK-SAME: in io_out__bore: !firrtl.uint<1> - %foo_io = firrtl.instance foo interesting_name @Foo(out io: !firrtl.bundle>) - %1 = firrtl.subfield %foo_io[out] : !firrtl.bundle> - firrtl.matchingconnect %0, %1 : !firrtl.uint<1> - } - // CHECK: firrtl.module @FooBar - firrtl.module @FooBar(out %io: !firrtl.bundle, out: uint<1>>) { - %0 = firrtl.subfield %io[out] : !firrtl.bundle, out: uint<1>> - // CHECK: firrtl.instance bar - // CHECK-SAME: in foo_io_out__bore: !firrtl.uint<1> - %bar_io = firrtl.instance bar interesting_name @Bar(out io: !firrtl.bundle>) - %1 = firrtl.subfield %bar_io[out] : !firrtl.bundle> - firrtl.matchingconnect %0, %1 : !firrtl.uint<1> - } -} - -// ----- - -// Test the behaviour of single source, multiple sink -// CHECK-LABEL: firrtl.circuit "FooBar" -firrtl.circuit "FooBar" attributes { - rawAnnotations = [ - { - class = "firrtl.passes.wiring.SourceAnnotation", - target = "FooBar.FooBar.io.in", - pin = "in" - }, - { - class = "firrtl.passes.wiring.SinkAnnotation", - target = "FooBar.Foo.io.out", - pin = "in" - }, - { - class = "firrtl.passes.wiring.SinkAnnotation", - target = "FooBar.Foo_1.io.out", - pin = "in" - }, - { - class = "firrtl.passes.wiring.SinkAnnotation", - target = "FooBar.Bar.io.out", - pin = "in" - }]} { - // CHECK: firrtl.module private @Foo - // CHECK-SAME: in %io_out__bore: !firrtl.uint<1> - firrtl.module private @Foo(out %io: !firrtl.bundle>) { - firrtl.skip - // CHECK: %0 = firrtl.subfield %io[out] : !firrtl.bundle> - // CHECK: firrtl.matchingconnect %0, %io_out__bore : !firrtl.uint<1> - } - // CHECK: firrtl.module private @Foo_1 - // CHECK-SAME: in %io_out__bore: !firrtl.uint<1> - firrtl.module private @Foo_1(out %io: !firrtl.bundle>) { - firrtl.skip - // CHECK: %0 = firrtl.subfield %io[out] : !firrtl.bundle> - // CHECK: firrtl.matchingconnect %0, %io_out__bore : !firrtl.uint<1> - } - // CHECK: firrtl.module private @Bar - // CHECK-SAME: in %io_out__bore: !firrtl.uint<1> - firrtl.module private @Bar(out %io: !firrtl.bundle>) { - firrtl.skip - // CHECK: %0 = firrtl.subfield %io[out] : !firrtl.bundle> - // CHECK: firrtl.matchingconnect %0, %io_out__bore : !firrtl.uint<1> - } - // CHECK: firrtl.module @FooBar - firrtl.module @FooBar(out %io: !firrtl.bundle, out_foo0: uint<1>, out_foo1: uint<1>, out_bar: uint<1>>) { - // CHECK: %0 = firrtl.subfield %io[in] : !firrtl.bundle, out_foo0: uint<1>, out_foo1: uint<1>, out_bar: uint<1>> - %0 = firrtl.subfield %io[out_bar] : !firrtl.bundle, out_foo0: uint<1>, out_foo1: uint<1>, out_bar: uint<1>> - %1 = firrtl.subfield %io[out_foo1] : !firrtl.bundle, out_foo0: uint<1>, out_foo1: uint<1>, out_bar: uint<1>> - %2 = firrtl.subfield %io[out_foo0] : !firrtl.bundle, out_foo0: uint<1>, out_foo1: uint<1>, out_bar: uint<1>> - // CHECK: firrtl.instance foo0 - // CHECK-SAME: in io_out__bore: !firrtl.uint<1> - %foo0_io = firrtl.instance foo0 interesting_name @Foo(out io: !firrtl.bundle>) - %3 = firrtl.subfield %foo0_io[out] : !firrtl.bundle> - // CHECK: firrtl.instance foo1 - // CHECK-SAME: in io_out__bore: !firrtl.uint<1> - %foo1_io = firrtl.instance foo1 interesting_name @Foo_1(out io: !firrtl.bundle>) - %4 = firrtl.subfield %foo1_io[out] : !firrtl.bundle> - // CHECK: firrtl.instance bar - // CHECK-SAME: in io_out__bore: !firrtl.uint<1> - %bar_io = firrtl.instance bar interesting_name @Bar(out io: !firrtl.bundle>) - %5 = firrtl.subfield %bar_io[out] : !firrtl.bundle> - firrtl.matchingconnect %2, %3 : !firrtl.uint<1> - firrtl.matchingconnect %1, %4 : !firrtl.uint<1> - firrtl.matchingconnect %0, %5 : !firrtl.uint<1> - // CHECK: firrtl.matchingconnect %foo0_io_out__bore, %0 : !firrtl.uint<1> - // CHECK: firrtl.matchingconnect %foo1_io_out__bore, %0 : !firrtl.uint<1> - // CHECK: firrtl.matchingconnect %bar_io_out__bore, %0 : !firrtl.uint<1> - } -} - -// ----- - -// CHECK-LABEL: circuit "Sub" -firrtl.circuit "Sub" attributes { - rawAnnotations = [ - { - class = "firrtl.passes.wiring.SourceAnnotation", - target = "Sub.Sub.a[0]", - pin = "test" - }, - { - class = "firrtl.passes.wiring.SinkAnnotation", - target = "Sub.Sub.b[0]", - pin = "test" - }]} { - firrtl.module @Sub() { - // CHECK: %[[a:.+]] = firrtl.wire - // CHECK-NEXT: %[[a_0:.+]] = firrtl.subindex %[[a]][0] - // CHECK: %[[b:.+]] = firrtl.wire - // CHECK-NEXT: %[[b_0:.+]] = firrtl.subindex %[[b]][0] - %a = firrtl.wire interesting_name : !firrtl.vector,1> - %b = firrtl.wire interesting_name : !firrtl.vector,1> - } -} - -// ----- - -// https://github.com/llvm/circt/issues/4651 -// Check that wiring can convert compatible types that can normally be connected. - -firrtl.circuit "ResetToI1" attributes { - rawAnnotations = [ - { - class = "firrtl.passes.wiring.SourceAnnotation", - target = "~ResetToI1|Bar>y", - pin = "xyz" - }, - { - class = "firrtl.passes.wiring.SinkAnnotation", - target = "~ResetToI1|ResetToI1>x", - pin = "xyz" - } - ]} { - firrtl.module private @Bar() { - %y = firrtl.wire interesting_name : !firrtl.reset - %invalid_reset = firrtl.invalidvalue : !firrtl.reset - firrtl.matchingconnect %y, %invalid_reset : !firrtl.reset - } - // CHECK-LABEL: module @ResetToI1 - firrtl.module @ResetToI1() { - // CHECK: %[[r1:.+]] = firrtl.resetCast %{{[^ ]*}} - // CHECK-NEXT: firrtl.matchingconnect %x, %[[r1]] : !firrtl.uint<1> - firrtl.instance bar interesting_name @Bar() - %x = firrtl.wire interesting_name : !firrtl.uint<1> - %invalid_ui1 = firrtl.invalidvalue : !firrtl.uint<1> - firrtl.matchingconnect %x, %invalid_ui1 : !firrtl.uint<1> - } -} - -// ----- - -// Similarly, but for integer types. - -firrtl.circuit "IntWidths" attributes { - rawAnnotations = [ - { - class = "firrtl.passes.wiring.SourceAnnotation", - target = "~IntWidths|Bar>y", - pin = "xyz" - }, - { - class = "firrtl.passes.wiring.SinkAnnotation", - target = "~IntWidths|IntWidths>x", - pin = "xyz" - } - ]} { - firrtl.module private @Bar() { - %y = firrtl.wire interesting_name : !firrtl.uint<4> - %invalid_reset = firrtl.invalidvalue : !firrtl.uint<4> - firrtl.matchingconnect %y, %invalid_reset : !firrtl.uint<4> - } - // CHECK-LABEL: module @IntWidths - firrtl.module @IntWidths() { - // CHECK: firrtl.connect %x, %{{[^ ]*}} : !firrtl.uint, !firrtl.uint<4> - firrtl.instance bar interesting_name @Bar() - %x = firrtl.wire interesting_name : !firrtl.uint - %invalid_ui1 = firrtl.invalidvalue : !firrtl.uint - firrtl.connect %x, %invalid_ui1 : !firrtl.uint, !firrtl.uint - } -} - -// ----- - -// Check direction of compatibility using const/non-const issue encountered (#6819). -firrtl.circuit "Issue6819" attributes { - rawAnnotations = [ - { - class = "firrtl.passes.wiring.SourceAnnotation", - target = "~Issue6819|Bar>y", - pin = "xyz" - }, - { - class = "firrtl.passes.wiring.SinkAnnotation", - target = "~Issue6819|Issue6819>x", - pin = "xyz" - } - ]} { - firrtl.module private @Bar() { - %y = firrtl.wire interesting_name : !firrtl.const.uint<4> - } - // CHECK-LABEL: module @Issue6819 - firrtl.module @Issue6819() { - // CHECK: firrtl.connect %x, %{{[^ ]*}} : !firrtl.uint, !firrtl.const.uint<4> - firrtl.instance bar interesting_name @Bar() - %x = firrtl.wire interesting_name : !firrtl.uint - %invalid_ui1 = firrtl.invalidvalue : !firrtl.uint - firrtl.connect %x, %invalid_ui1 : !firrtl.uint, !firrtl.uint - } -}