diff --git a/.vscode/tasks.json b/.vscode/tasks.json index 358b0eba0..50ef41d7b 100644 --- a/.vscode/tasks.json +++ b/.vscode/tasks.json @@ -206,6 +206,15 @@ "CMake: configure" ], "command": "cmake --build --preset ${command:cmake.activeBuildPresetName} --target CAN_STRESS_TEST" + }, + { + "label": "CMake: configure and build CAN_LOOPBACK_TEST", + "type": "shell", + "dependsOrder": "sequence", + "dependsOn": [ + "CMake: configure" + ], + "command": "cmake --build --preset ${command:cmake.activeBuildPresetName} --target CAN_LOOPBACK_TEST" } ] } diff --git a/CMakeLists.txt b/CMakeLists.txt index c78af7f6e..c8e0d086f 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -54,6 +54,8 @@ include("Autogen/CAN/CANfigurator.cmake") # Peripherals include("${lib_path}/Peripherals/USART/common.cmake") include("${lib_path}/Peripherals/CAN/common.cmake") + +include("${lib_path}/FancyLayers-RENAME/GRCAN/grcan_fancylayer.cmake") include("${lib_path}/FancyLayers-RENAME/ADC/adc.cmake") include("${lib_path}/FancyLayers-RENAME/NeoPixel/neopixel.cmake") @@ -89,6 +91,7 @@ add_gr_project(STM32G474xE G4CANTESTING CAN_INTERNAL_TEST) add_gr_project(STM32G474xE G4CANTESTING CAN_RELEASE_TEST) add_gr_project(STM32G474xE G4CANTESTING CAN_STRESS_TEST) add_gr_project(STM32G474xE G4CANTESTING CAN_FILTER_TEST) +add_gr_project(STM32G474xE G4FANCYCANTESTING CAN_LOOPBACK_TEST) add_gr_project(STM32G474xE G4NEOTESTING) diff --git a/G4FANCYCANTESTING/CAN_LOOPBACK_TEST/CMakeLists.txt b/G4FANCYCANTESTING/CAN_LOOPBACK_TEST/CMakeLists.txt new file mode 100644 index 000000000..0ab707beb --- /dev/null +++ b/G4FANCYCANTESTING/CAN_LOOPBACK_TEST/CMakeLists.txt @@ -0,0 +1,60 @@ +cmake_minimum_required(VERSION 3.25) + +# Setup compiler settings +set(CMAKE_C_STANDARD 11) +set(CMAKE_C_STANDARD_REQUIRED ON) +set(CMAKE_C_EXTENSIONS ON) + +# Define the build type +if(NOT CMAKE_BUILD_TYPE) + set(CMAKE_BUILD_TYPE "Debug") +endif() + +# Enable compile command to ease indexing with e.g. clangd +set(CMAKE_EXPORT_COMPILE_COMMANDS TRUE) + +# Enable CMake support for ASM and C languages +enable_language( + C + ASM +) + +# Core project settings +project(${CMAKE_PROJECT_NAME}) + +# what, does in fact not get the filename of somthing but rather the name of the project from the path +get_filename_component(PROJECT_NAME ${CMAKE_CURRENT_SOURCE_DIR} NAME) + +add_library(${PROJECT_NAME}_USER_CODE INTERFACE) + +target_sources( + ${PROJECT_NAME}_USER_CODE + INTERFACE + ../Core/Src/adc.c + ../Core/Src/crc.c + ../Core/Src/dma.c + ../Core/Src/gpio.c + ../Core/Src/i2c.c + main.c + ../Core/Src/spi.c + ../Core/Src/stm32g4xx_hal_msp.c + ../Core/Src/stm32g4xx_it.c + ../Core/Src/tim.c + ../Core/Src/usart.c +) + +set_target_properties( + ${NAME} + PROPERTIES + OUTPUT_NAME + "CAN_${NAME}" +) + +target_link_libraries(${PROJECT_NAME}_USER_CODE INTERFACE GRCAN_FANCYLAYER) + +target_include_directories( + ${PROJECT_NAME}_USER_CODE + INTERFACE + ../Core/Inc + . +) diff --git a/G4FANCYCANTESTING/CAN_LOOPBACK_TEST/can_cfg.h b/G4FANCYCANTESTING/CAN_LOOPBACK_TEST/can_cfg.h new file mode 100644 index 000000000..8a18e8882 --- /dev/null +++ b/G4FANCYCANTESTING/CAN_LOOPBACK_TEST/can_cfg.h @@ -0,0 +1,10 @@ +#ifndef CAN_CFG_H +#define CAN_CFG_H + +#define USECAN1 +#define TX_BUFFER_1_SIZE 10 + +#define USECAN2 +#define TX_BUFFER_2_SIZE 10 + +#endif diff --git a/G4FANCYCANTESTING/CAN_LOOPBACK_TEST/main.c b/G4FANCYCANTESTING/CAN_LOOPBACK_TEST/main.c new file mode 100644 index 000000000..0e46a98e6 --- /dev/null +++ b/G4FANCYCANTESTING/CAN_LOOPBACK_TEST/main.c @@ -0,0 +1,274 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +#include "adc.h" +#include "can.h" // Assume this works +#include "can_tests.h" +#include "dma.h" +#include "fdcan.h" +#include "gpio.h" +#include "i2c.h" +#include "spi.h" +#include "tim.h" +#include "usart.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "Logomatic.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/* Enable ITM for SWO output */ +static void ITM_Enable(void) +{ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + GPIO_InitStruct.Pin = LL_GPIO_PIN_3; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_0; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + DBGMCU->CR |= DBGMCU_CR_TRACE_IOEN; + + /* Enable TRC (Trace) */ + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + + /* Configure TPI for SWO output (set prescaler for 2MHz SWO clock) */ + TPI->SPPR = 2U; /* 2 = Manchester/async UART mode */ + TPI->ACPR = 84U; /* Prescaler: (170 MHz / (84+1) / 2) ≈ 1MHz SWO */ + + ITM->TER |= (1UL << 0); + ITM->TCR |= (ITM_TCR_ITMENA_Msk | ITM_TCR_SWOENA_Msk); +} +// static int toggleze = 0; +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU + * Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the + * Systick. */ + HAL_Init(); + /* USER CODE BEGIN Init */ + ITM_Enable(); + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_DMA_Init(); + // MX_FDCAN2_Init(); + MX_ADC1_Init(); + MX_LPUART1_UART_Init(); + MX_I2C2_Init(); + MX_USART1_UART_Init(); + MX_SPI3_Init(); + MX_TIM2_Init(); + + /* USER CODE BEGIN 2 */ + + LOGOMATIC("Booted!\n"); + + // LOGOMATIC("running can_external_test:\n"); + can_external_test(); + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) { + /* USER CODE END WHILE */ + LOGOMATIC("Main Loop\n"); + LL_mDelay(1000); + + // Receive on GPIOs + // HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, toggleze ? GPIO_PIN_SET + // : GPIO_PIN_RESET); HAL_Delay(1000); msg.data[0] = toggleze ? + // 0x00 : 0x80; can_send(data_can, &msg); + + // RCC->CFGR |= RCC_CFGR_SW; + /* USER CODE BEGIN 3 */ + } +} + +/** + * @brief System Clock Configuration + * @retval None + */ + +// void SystemClock_Config(void) +// { +// LL_FLASH_SetLatency(LL_FLASH_LATENCY_4); +// while (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_4) { +// } +// LL_PWR_EnableRange1BoostMode(); +// LL_RCC_HSE_Enable(); + +// /* Wait till HSE is ready */ +// while (LL_RCC_HSE_IsReady() != 1) { +// } + +// LL_RCC_HSE_EnableCSS(); +// LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_1, 20, +// LL_RCC_PLLR_DIV_2); +// //LL_RCC_PLL_ConfigDomain_48M(LL_RCC_PLLSOURCE_HSE, ); +// LL_RCC_PLL_EnableDomain_SYS(); +// LL_RCC_PLL_Enable(); +// /* Wait till PLL is ready */ +// while (LL_RCC_PLL_IsReady() != 1) { +// } + +// LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); +// LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2); +// /* Wait till System clock is ready */ +// while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) { +// } + +// /* Insure 1us transition state at intermediate medium speed clock*/ +// for (__IO uint32_t i = (170 >> 1); i != 0; i--) +// ; + +// /* Set AHB prescaler*/ +// LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); +// LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); +// LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); +// LL_SetSystemCoreClock(160000000); + +// /* Update the time base */ +// if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) { +// Error_Handler(); +// } +// }*/ +void SystemClock_Config(void) +{ + LL_FLASH_SetLatency(LL_FLASH_LATENCY_4); + while (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_4) {} + LL_PWR_EnableRange1BoostMode(); + LL_RCC_HSI_Enable(); + /* Wait till HSI is ready */ + while (LL_RCC_HSI_IsReady() != 1) {} + + LL_RCC_HSI_SetCalibTrimming(64); + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLM_DIV_4, 85, LL_RCC_PLLR_DIV_2); + LL_RCC_PLL_EnableDomain_SYS(); + LL_RCC_PLL_Enable(); + /* Wait till PLL is ready */ + while (LL_RCC_PLL_IsReady() != 1) {} + + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + // LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + /* Wait till System clock is ready */ + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {} + + /* Insure 1us transition state at intermediate medium speed clock*/ + for (__IO uint32_t i = (170 >> 1); i != 0; i--) + ; + + /* Set AHB prescaler*/ + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1); + LL_SetSystemCoreClock(170000000); + + /* Update the time base */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) { + Error_Handler(); + } +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return + * state */ + __disable_irq(); + while (1) {} + /* USER CODE END Error_Handler_Debug */ +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line + number, ex: printf("Wrong parameters value: file %s on line %d\r\n", + file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/G4FANCYCANTESTING/Core/Inc/adc.h b/G4FANCYCANTESTING/Core/Inc/adc.h new file mode 100644 index 000000000..41154538b --- /dev/null +++ b/G4FANCYCANTESTING/Core/Inc/adc.h @@ -0,0 +1,49 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file adc.h + * @brief This file contains all the function prototypes for + * the adc.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __ADC_H__ +#define __ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_ADC1_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_H__ */ diff --git a/G4FANCYCANTESTING/Core/Inc/crc.h b/G4FANCYCANTESTING/Core/Inc/crc.h new file mode 100644 index 000000000..133957e92 --- /dev/null +++ b/G4FANCYCANTESTING/Core/Inc/crc.h @@ -0,0 +1,51 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file crc.h + * @brief This file contains all the function prototypes for + * the crc.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CRC_H__ +#define __CRC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern CRC_HandleTypeDef hcrc; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_CRC_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CRC_H__ */ diff --git a/G4FANCYCANTESTING/Core/Inc/dma.h b/G4FANCYCANTESTING/Core/Inc/dma.h new file mode 100644 index 000000000..ae819cab4 --- /dev/null +++ b/G4FANCYCANTESTING/Core/Inc/dma.h @@ -0,0 +1,51 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.h + * @brief This file contains all the function prototypes for + * the dma.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DMA_H__ +#define __DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* DMA memory to memory transfer handles -------------------------------------*/ + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_DMA_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_H__ */ diff --git a/G4FANCYCANTESTING/Core/Inc/fdcan.h b/G4FANCYCANTESTING/Core/Inc/fdcan.h new file mode 100644 index 000000000..56c4a8adb --- /dev/null +++ b/G4FANCYCANTESTING/Core/Inc/fdcan.h @@ -0,0 +1,51 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file fdcan.h + * @brief This file contains all the function prototypes for + * the fdcan.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FDCAN_H__ +#define __FDCAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern FDCAN_HandleTypeDef hfdcan2; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_FDCAN2_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FDCAN_H__ */ diff --git a/G4FANCYCANTESTING/Core/Inc/gpio.h b/G4FANCYCANTESTING/Core/Inc/gpio.h new file mode 100644 index 000000000..843d4e9e7 --- /dev/null +++ b/G4FANCYCANTESTING/Core/Inc/gpio.h @@ -0,0 +1,48 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ GPIO_H__ */ diff --git a/G4FANCYCANTESTING/Core/Inc/i2c.h b/G4FANCYCANTESTING/Core/Inc/i2c.h new file mode 100644 index 000000000..0a0a50803 --- /dev/null +++ b/G4FANCYCANTESTING/Core/Inc/i2c.h @@ -0,0 +1,49 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file i2c.h + * @brief This file contains all the function prototypes for + * the i2c.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_I2C2_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __I2C_H__ */ diff --git a/G4FANCYCANTESTING/Core/Inc/main.h b/G4FANCYCANTESTING/Core/Inc/main.h new file mode 100644 index 000000000..23d7ffce4 --- /dev/null +++ b/G4FANCYCANTESTING/Core/Inc/main.h @@ -0,0 +1,115 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal.h" +#include "stm32g4xx_ll_adc.h" +#include "stm32g4xx_ll_bus.h" +#include "stm32g4xx_ll_cortex.h" +#include "stm32g4xx_ll_crs.h" +#include "stm32g4xx_ll_dma.h" +#include "stm32g4xx_ll_exti.h" +#include "stm32g4xx_ll_gpio.h" +#include "stm32g4xx_ll_i2c.h" +#include "stm32g4xx_ll_lpuart.h" +#include "stm32g4xx_ll_pwr.h" +#include "stm32g4xx_ll_rcc.h" +#include "stm32g4xx_ll_spi.h" +#include "stm32g4xx_ll_system.h" +#include "stm32g4xx_ll_tim.h" +#include "stm32g4xx_ll_usart.h" +#include "stm32g4xx_ll_utils.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define BSPD_SIGNAL_Pin LL_GPIO_PIN_1 +#define BSPD_SIGNAL_GPIO_Port GPIOC +#define APPS1_SIGNAL_Pin LL_GPIO_PIN_2 +#define APPS1_SIGNAL_GPIO_Port GPIOC +#define APPS2_SIGNAL_Pin LL_GPIO_PIN_3 +#define APPS2_SIGNAL_GPIO_Port GPIOC +#define BLINKY_Pin LL_GPIO_PIN_5 +#define BLINKY_GPIO_Port GPIOA +#define IMD_SENSE_Pin LL_GPIO_PIN_6 +#define IMD_SENSE_GPIO_Port GPIOA +#define AMS_SENSE_Pin LL_GPIO_PIN_7 +#define AMS_SENSE_GPIO_Port GPIOA +#define BRAKE_F_SIGNAL_Pin LL_GPIO_PIN_0 +#define BRAKE_F_SIGNAL_GPIO_Port GPIOB +#define BRAKE_R_SIGNAL_Pin LL_GPIO_PIN_1 +#define BRAKE_R_SIGNAL_GPIO_Port GPIOB +#define LED_TEST_Pin LL_GPIO_PIN_11 +#define LED_TEST_GPIO_Port GPIOB +#define AUX_SIGNAL_Pin LL_GPIO_PIN_14 +#define AUX_SIGNAL_GPIO_Port GPIOB +#define STEERING_ANGLE_Pin LL_GPIO_PIN_15 +#define STEERING_ANGLE_GPIO_Port GPIOB +#define BRAKE_LIGHT_Pin LL_GPIO_PIN_4 +#define BRAKE_LIGHT_GPIO_Port GPIOB +#define TSSI_G_CONTROL_Pin LL_GPIO_PIN_5 +#define TSSI_G_CONTROL_GPIO_Port GPIOB +#define AUX_CONTROL_Pin LL_GPIO_PIN_8 +#define AUX_CONTROL_GPIO_Port GPIOB +#define SOFTWARE_OK_CONTROL_Pin LL_GPIO_PIN_9 +#define SOFTWARE_OK_CONTROL_GPIO_Port GPIOB + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/G4FANCYCANTESTING/Core/Inc/spi.h b/G4FANCYCANTESTING/Core/Inc/spi.h new file mode 100644 index 000000000..74bed003b --- /dev/null +++ b/G4FANCYCANTESTING/Core/Inc/spi.h @@ -0,0 +1,49 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file spi.h + * @brief This file contains all the function prototypes for + * the spi.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPI_H__ +#define __SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_SPI3_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPI_H__ */ diff --git a/G4FANCYCANTESTING/Core/Inc/stm32g4xx_hal_conf.h b/G4FANCYCANTESTING/Core/Inc/stm32g4xx_hal_conf.h new file mode 100644 index 000000000..3e1fcb018 --- /dev/null +++ b/G4FANCYCANTESTING/Core/Inc/stm32g4xx_hal_conf.h @@ -0,0 +1,390 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g4xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G4xx_HAL_CONF_H +#define STM32G4xx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ + +#define HAL_MODULE_ENABLED + +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CORDIC_MODULE_ENABLED */ +#define HAL_CRC_MODULE_ENABLED +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +#define HAL_FDCAN_MODULE_ENABLED +/*#define HAL_FMAC_MODULE_ENABLED */ +/*#define HAL_HRTIM_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_I2C_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_OPAMP_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_QSPI_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_UART_MODULE_ENABLED */ +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Register Callbacks selection + * ############################## */ +/** + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + +/* ########################## Oscillator Values adaptation + * ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your + * application. This value is used by the RCC HAL module to compute the system + * frequency (when HSE is used as system clock source, directly or through the + * PLL). + */ +#if !defined(HSE_VALUE) +#define HSE_VALUE (16000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined(HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system + * frequency (when HSI is used as system clock source, directly or through the + * PLL). + */ +#if !defined(HSI_VALUE) +#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. + * This internal oscillator is mainly dedicated to provide a high + * precision clock to the USB peripheral by means of a special Clock Recovery + * System (CRS) circuitry. When the CRS is not used, the HSI48 RC oscillator + * runs on it default frequency which is subject to manufacturing process + * variations. + */ +#if !defined(HSI48_VALUE) +#define HSI48_VALUE \ + (48000000UL) /*!< Value of the Internal High Speed oscillator for USB \ + FS/RNG in Hz. The real value my vary depending on \ + manufacturing process variations.*/ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined(LSI_VALUE) +/*!< Value of the Internal Low Speed oscillator in Hz +The real value may vary depending on the variations in voltage and +temperature.*/ +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system + * frequency + */ +#if !defined(LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined(LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S and SAI peripherals + * This value is used by the I2S and SAI HAL modules to compute the I2S + * and SAI clock source frequency, this source is inserted directly through + * I2S_CKIN pad. + */ +#if !defined(EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ + +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32g4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32g4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32g4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32g4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32g4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED +#include "stm32g4xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED +#include "stm32g4xx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32g4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32g4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED +#include "stm32g4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32g4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32g4xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32g4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_FMAC_MODULE_ENABLED +#include "stm32g4xx_hal_fmac.h" +#endif /* HAL_FMAC_MODULE_ENABLED */ + +#ifdef HAL_HRTIM_MODULE_ENABLED +#include "stm32g4xx_hal_hrtim.h" +#endif /* HAL_HRTIM_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32g4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32g4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32g4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED +#include "stm32g4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32g4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32g4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED +#include "stm32g4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED +#include "stm32g4xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32g4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32g4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED +#include "stm32g4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32g4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32g4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32g4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32g4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32g4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32g4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED +#include "stm32g4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32g4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32g4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32g4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32g4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G4xx_HAL_CONF_H */ diff --git a/G4FANCYCANTESTING/Core/Inc/stm32g4xx_it.h b/G4FANCYCANTESTING/Core/Inc/stm32g4xx_it.h new file mode 100644 index 000000000..b6c3b2f72 --- /dev/null +++ b/G4FANCYCANTESTING/Core/Inc/stm32g4xx_it.h @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32G4xx_IT_H +#define __STM32G4xx_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void FDCAN2_IT0_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32G4xx_IT_H */ diff --git a/G4FANCYCANTESTING/Core/Inc/tim.h b/G4FANCYCANTESTING/Core/Inc/tim.h new file mode 100644 index 000000000..c19e6cc71 --- /dev/null +++ b/G4FANCYCANTESTING/Core/Inc/tim.h @@ -0,0 +1,49 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.h + * @brief This file contains all the function prototypes for + * the tim.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TIM_H__ +#define __TIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_TIM2_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_H__ */ diff --git a/G4FANCYCANTESTING/Core/Inc/usart.h b/G4FANCYCANTESTING/Core/Inc/usart.h new file mode 100644 index 000000000..daefd73e6 --- /dev/null +++ b/G4FANCYCANTESTING/Core/Inc/usart.h @@ -0,0 +1,50 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.h + * @brief This file contains all the function prototypes for + * the usart.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USART_H__ +#define __USART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_LPUART1_UART_Init(void); +void MX_USART1_UART_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USART_H__ */ diff --git a/G4FANCYCANTESTING/Core/Src/adc.c b/G4FANCYCANTESTING/Core/Src/adc.c new file mode 100644 index 000000000..f3dbff8ed --- /dev/null +++ b/G4FANCYCANTESTING/Core/Src/adc.c @@ -0,0 +1,186 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file adc.c + * @brief This file provides code for the configuration + * of the ADC instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "adc.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* ADC1 init function */ +void MX_ADC1_Init(void) +{ + + /* USER CODE BEGIN ADC1_Init 0 */ + + /* USER CODE END ADC1_Init 0 */ + + LL_ADC_InitTypeDef ADC_InitStruct = {0}; + LL_ADC_REG_InitTypeDef ADC_REG_InitStruct = {0}; + LL_ADC_CommonInitTypeDef ADC_CommonInitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + LL_RCC_SetADCClockSource(LL_RCC_ADC12_CLKSOURCE_SYSCLK); + + /* Peripheral clock enable */ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC12); + + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); + /**ADC1 GPIO Configuration + PC1 ------> ADC1_IN7 + PC2 ------> ADC1_IN8 + PC3 ------> ADC1_IN9 + PB0 ------> ADC1_IN15 + PB1 ------> ADC1_IN12 + PB14 ------> ADC1_IN5 + */ + GPIO_InitStruct.Pin = BSPD_SIGNAL_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(BSPD_SIGNAL_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = APPS1_SIGNAL_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(APPS1_SIGNAL_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = APPS2_SIGNAL_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(APPS2_SIGNAL_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = BRAKE_F_SIGNAL_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(BRAKE_F_SIGNAL_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = BRAKE_R_SIGNAL_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(BRAKE_R_SIGNAL_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = AUX_SIGNAL_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(AUX_SIGNAL_GPIO_Port, &GPIO_InitStruct); + + /* ADC1 DMA Init */ + + /* ADC1 Init */ + LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_ADC1); + + LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_1, LL_DMA_DIRECTION_PERIPH_TO_MEMORY); + + LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PRIORITY_LOW); + + LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MODE_CIRCULAR); + + LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PERIPH_NOINCREMENT); + + LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MEMORY_INCREMENT); + + LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PDATAALIGN_HALFWORD); + + LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MDATAALIGN_HALFWORD); + + /* USER CODE BEGIN ADC1_Init 1 */ + + /* USER CODE END ADC1_Init 1 */ + + /** Common config + */ + ADC_InitStruct.Resolution = LL_ADC_RESOLUTION_12B; + ADC_InitStruct.DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; + ADC_InitStruct.LowPowerMode = LL_ADC_LP_MODE_NONE; + LL_ADC_Init(ADC1, &ADC_InitStruct); + ADC_REG_InitStruct.TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; + ADC_REG_InitStruct.SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS; + ADC_REG_InitStruct.SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; + ADC_REG_InitStruct.ContinuousMode = LL_ADC_REG_CONV_CONTINUOUS; + ADC_REG_InitStruct.DMATransfer = LL_ADC_REG_DMA_TRANSFER_UNLIMITED; + ADC_REG_InitStruct.Overrun = LL_ADC_REG_OVR_DATA_PRESERVED; + LL_ADC_REG_Init(ADC1, &ADC_REG_InitStruct); + LL_ADC_SetGainCompensation(ADC1, 0); + LL_ADC_SetOverSamplingScope(ADC1, LL_ADC_OVS_DISABLE); + ADC_CommonInitStruct.CommonClock = LL_ADC_CLOCK_ASYNC_DIV256; + ADC_CommonInitStruct.Multimode = LL_ADC_MULTI_INDEPENDENT; + LL_ADC_CommonInit(__LL_ADC_COMMON_INSTANCE(ADC1), &ADC_CommonInitStruct); + + /* Disable ADC deep power down (enabled by default after reset state) */ + LL_ADC_DisableDeepPowerDown(ADC1); + /* Enable ADC internal voltage regulator */ + LL_ADC_EnableInternalRegulator(ADC1); + /* Delay for ADC internal voltage regulator stabilization. */ + /* Compute number of CPU cycles to wait for, from delay in us. */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles (depends on compilation optimization). */ + /* Note: If system core clock frequency is below 200kHz, wait time */ + /* is only a few CPU processing cycles. */ + uint32_t wait_loop_index; + wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (100000 * 2))) / 10); + while (wait_loop_index != 0) { + wait_loop_index--; + } + + /** Configure Regular Channel + */ + LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_1, LL_ADC_CHANNEL_5); + LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_5, LL_ADC_SAMPLINGTIME_92CYCLES_5); + LL_ADC_SetChannelSingleDiff(ADC1, LL_ADC_CHANNEL_5, LL_ADC_SINGLE_ENDED); + + /** Configure Regular Channel + */ + LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_2, LL_ADC_CHANNEL_7); + LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_7, LL_ADC_SAMPLINGTIME_92CYCLES_5); + LL_ADC_SetChannelSingleDiff(ADC1, LL_ADC_CHANNEL_7, LL_ADC_SINGLE_ENDED); + + /** Configure Regular Channel + */ + LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_3, LL_ADC_CHANNEL_8); + LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_8, LL_ADC_SAMPLINGTIME_92CYCLES_5); + LL_ADC_SetChannelSingleDiff(ADC1, LL_ADC_CHANNEL_8, LL_ADC_SINGLE_ENDED); + + /** Configure Regular Channel + */ + LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_4, LL_ADC_CHANNEL_9); + LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_9, LL_ADC_SAMPLINGTIME_92CYCLES_5); + LL_ADC_SetChannelSingleDiff(ADC1, LL_ADC_CHANNEL_9, LL_ADC_SINGLE_ENDED); + + /** Configure Regular Channel + */ + LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_5, LL_ADC_CHANNEL_12); + LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_12, LL_ADC_SAMPLINGTIME_92CYCLES_5); + LL_ADC_SetChannelSingleDiff(ADC1, LL_ADC_CHANNEL_12, LL_ADC_SINGLE_ENDED); + + /** Configure Regular Channel + */ + LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_6, LL_ADC_CHANNEL_15); + LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_15, LL_ADC_SAMPLINGTIME_92CYCLES_5); + LL_ADC_SetChannelSingleDiff(ADC1, LL_ADC_CHANNEL_15, LL_ADC_SINGLE_ENDED); + /* USER CODE BEGIN ADC1_Init 2 */ + + /* USER CODE END ADC1_Init 2 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/G4FANCYCANTESTING/Core/Src/crc.c b/G4FANCYCANTESTING/Core/Src/crc.c new file mode 100644 index 000000000..213510a5d --- /dev/null +++ b/G4FANCYCANTESTING/Core/Src/crc.c @@ -0,0 +1,86 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file crc.c + * @brief This file provides code for the configuration + * of the CRC instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "crc.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +CRC_HandleTypeDef hcrc; + +/* CRC init function */ +void MX_CRC_Init(void) +{ + + /* USER CODE BEGIN CRC_Init 0 */ + + /* USER CODE END CRC_Init 0 */ + + /* USER CODE BEGIN CRC_Init 1 */ + + /* USER CODE END CRC_Init 1 */ + hcrc.Instance = CRC; + hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE; + hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE; + hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE; + hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE; + hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; + if (HAL_CRC_Init(&hcrc) != HAL_OK) { + Error_Handler(); + } + /* USER CODE BEGIN CRC_Init 2 */ + + /* USER CODE END CRC_Init 2 */ +} + +void HAL_CRC_MspInit(CRC_HandleTypeDef *crcHandle) +{ + + if (crcHandle->Instance == CRC) { + /* USER CODE BEGIN CRC_MspInit 0 */ + + /* USER CODE END CRC_MspInit 0 */ + /* CRC clock enable */ + __HAL_RCC_CRC_CLK_ENABLE(); + /* USER CODE BEGIN CRC_MspInit 1 */ + + /* USER CODE END CRC_MspInit 1 */ + } +} + +void HAL_CRC_MspDeInit(CRC_HandleTypeDef *crcHandle) +{ + + if (crcHandle->Instance == CRC) { + /* USER CODE BEGIN CRC_MspDeInit 0 */ + + /* USER CODE END CRC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_CRC_CLK_DISABLE(); + /* USER CODE BEGIN CRC_MspDeInit 1 */ + + /* USER CODE END CRC_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/G4FANCYCANTESTING/Core/Src/dma.c b/G4FANCYCANTESTING/Core/Src/dma.c new file mode 100644 index 000000000..491e3889d --- /dev/null +++ b/G4FANCYCANTESTING/Core/Src/dma.c @@ -0,0 +1,50 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.c + * @brief This file provides code for the configuration + * of all the requested memory to memory DMA transfers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "dma.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure DMA */ +/*----------------------------------------------------------------------------*/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * Enable DMA controller clock + */ +void MX_DMA_Init(void) +{ + + /* Init with LL driver */ + /* DMA controller clock enable */ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1); + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1); +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ diff --git a/G4FANCYCANTESTING/Core/Src/fdcan.c b/G4FANCYCANTESTING/Core/Src/fdcan.c new file mode 100644 index 000000000..ebc13ea73 --- /dev/null +++ b/G4FANCYCANTESTING/Core/Src/fdcan.c @@ -0,0 +1,135 @@ +// #include "unused.h" +// /* USER CODE BEGIN Header */ +// /** +// ****************************************************************************** +// * @file fdcan.c +// * @brief This file provides code for the configuration +// * of the FDCAN instances. +// ****************************************************************************** +// * @attention +// * +// * Copyright (c) 2024 STMicroelectronics. +// * All rights reserved. +// * +// * This software is licensed under terms that can be found in the LICENSE file +// * in the root directory of this software component. +// * If no LICENSE file comes with this software, it is provided AS-IS. +// * +// ****************************************************************************** +// */ +// /* USER CODE END Header */ +// /* Includes ------------------------------------------------------------------*/ +// #include "fdcan.h" + +// /* USER CODE BEGIN 0 */ + +// /* USER CODE END 0 */ + +// FDCAN_HandleTypeDef hfdcan2; + +// /* FDCAN2 init function */ +// void MX_FDCAN2_Init(void) +// { + +// /* USER CODE BEGIN FDCAN2_Init 0 */ + +// /* USER CODE END FDCAN2_Init 0 */ + +// /* USER CODE BEGIN FDCAN2_Init 1 */ + +// /* USER CODE END FDCAN2_Init 1 */ +// hfdcan2.Instance = FDCAN2; +// hfdcan2.Init.ClockDivider = FDCAN_CLOCK_DIV1; +// hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC; +// hfdcan2.Init.Mode = FDCAN_MODE_NORMAL; +// hfdcan2.Init.AutoRetransmission = ENABLE; +// hfdcan2.Init.TransmitPause = DISABLE; +// hfdcan2.Init.ProtocolException = ENABLE; +// hfdcan2.Init.NominalPrescaler = 1; +// hfdcan2.Init.NominalSyncJumpWidth = 16; +// hfdcan2.Init.NominalTimeSeg1 = 119; +// hfdcan2.Init.NominalTimeSeg2 = 40; +// hfdcan2.Init.DataPrescaler = 8; +// hfdcan2.Init.DataSyncJumpWidth = 16; +// hfdcan2.Init.DataTimeSeg1 = 14; +// hfdcan2.Init.DataTimeSeg2 = 5; +// hfdcan2.Init.StdFiltersNbr = 0; +// hfdcan2.Init.ExtFiltersNbr = 2; +// hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; +// if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK) { +// Error_Handler(); +// } +// /* USER CODE BEGIN FDCAN2_Init 2 */ + +// /* USER CODE END FDCAN2_Init 2 */ +// } + +// void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *fdcanHandle) +// { + +// GPIO_InitTypeDef GPIO_InitStruct = {0}; +// if (fdcanHandle->Instance == FDCAN2) { +// /* USER CODE BEGIN FDCAN2_MspInit 0 */ + +// /* USER CODE END FDCAN2_MspInit 0 */ +// LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1); + +// /* FDCAN2 clock enable */ +// __HAL_RCC_FDCAN_CLK_ENABLE(); + +// __HAL_RCC_GPIOB_CLK_ENABLE(); +// /**FDCAN2 GPIO Configuration +// PB12 ------> FDCAN2_RX +// PB13 ------> FDCAN2_TX +// */ +// GPIO_InitStruct.Pin = GPIO_PIN_12; +// GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; +// GPIO_InitStruct.Pull = GPIO_PULLUP; +// GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; +// GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2; +// HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + +// GPIO_InitStruct.Pin = GPIO_PIN_13; +// GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; +// GPIO_InitStruct.Pull = GPIO_NOPULL; +// GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; +// GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2; +// HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + +// /* FDCAN2 interrupt Init */ +// HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 0, 0); +// HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn); +// /* USER CODE BEGIN FDCAN2_MspInit 1 */ + +// /* USER CODE END FDCAN2_MspInit 1 */ +// } +// } + +// /*void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *fdcanHandle) +// { + +// if (fdcanHandle->Instance == FDCAN2) { +// /* USER CODE BEGIN FDCAN2_MspDeInit 0 */ + +// /* USER CODE END FDCAN2_MspDeInit 0 */ +// /* Peripheral clock disable */ +// __HAL_RCC_FDCAN_CLK_DISABLE(); + +// /**FDCAN2 GPIO Configuration +// PB12 ------> FDCAN2_RX +// PB13 ------> FDCAN2_TX +// */ +// HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12 | GPIO_PIN_13); + +// /* FDCAN2 interrupt Deinit */ +// HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn); +// /* USER CODE BEGIN FDCAN2_MspDeInit 1 */ + +// /* USER CODE END FDCAN2_MspDeInit 1 */ +// } +// } + +// /* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +// UNUSED(5); diff --git a/G4FANCYCANTESTING/Core/Src/gpio.c b/G4FANCYCANTESTING/Core/Src/gpio.c new file mode 100644 index 000000000..d36e6eca6 --- /dev/null +++ b/G4FANCYCANTESTING/Core/Src/gpio.c @@ -0,0 +1,260 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** Configure pins as + * Analog + * Input + * Output + * EVENT_OUT + * EXTI + * Free pins are configured automatically as Analog (this feature is + enabled through + * the Code Generation settings) + PA6 ------> ADC2_IN3 + PA7 ------> ADC2_IN4 + PB15 ------> ADC2_IN15 + PB7 ------> UART4_CTS +*/ +void MX_GPIO_Init(void) +{ + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOF); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOG); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD); + + /**/ + LL_GPIO_ResetOutputPin(BLINKY_GPIO_Port, BLINKY_Pin); + + /**/ + LL_GPIO_ResetOutputPin(LED_TEST_GPIO_Port, LED_TEST_Pin); + + /**/ + LL_GPIO_ResetOutputPin(BRAKE_LIGHT_GPIO_Port, BRAKE_LIGHT_Pin); + + /**/ + LL_GPIO_ResetOutputPin(TSSI_G_CONTROL_GPIO_Port, TSSI_G_CONTROL_Pin); + + /**/ + LL_GPIO_ResetOutputPin(AUX_CONTROL_GPIO_Port, AUX_CONTROL_Pin); + + /**/ + LL_GPIO_ResetOutputPin(SOFTWARE_OK_CONTROL_GPIO_Port, SOFTWARE_OK_CONTROL_Pin); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_13; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_14; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_15; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_4; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = BLINKY_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(BLINKY_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = IMD_SENSE_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(IMD_SENSE_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = AMS_SENSE_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(AMS_SENSE_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_2; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LED_TEST_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(LED_TEST_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = STEERING_ANGLE_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(STEERING_ANGLE_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_8; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_9; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_9; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_15; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_2; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = BRAKE_LIGHT_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(BRAKE_LIGHT_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = TSSI_G_CONTROL_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(TSSI_G_CONTROL_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_14; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = AUX_CONTROL_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(AUX_CONTROL_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = SOFTWARE_OK_CONTROL_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(SOFTWARE_OK_CONTROL_GPIO_Port, &GPIO_InitStruct); +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ diff --git a/G4FANCYCANTESTING/Core/Src/i2c.c b/G4FANCYCANTESTING/Core/Src/i2c.c new file mode 100644 index 000000000..bfb4e0153 --- /dev/null +++ b/G4FANCYCANTESTING/Core/Src/i2c.c @@ -0,0 +1,92 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file i2c.c + * @brief This file provides code for the configuration + * of the I2C instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "i2c.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* I2C2 init function */ +void MX_I2C2_Init(void) +{ + + /* USER CODE BEGIN I2C2_Init 0 */ + + /* USER CODE END I2C2_Init 0 */ + + LL_I2C_InitTypeDef I2C_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + LL_RCC_SetI2CClockSource(LL_RCC_I2C2_CLKSOURCE_PCLK1); + + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); + /**I2C2 GPIO Configuration + PC4 ------> I2C2_SCL + PA8 ------> I2C2_SDA + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_4; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_4; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_8; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_4; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C2); + + /* USER CODE BEGIN I2C2_Init 1 */ + + /* USER CODE END I2C2_Init 1 */ + + /** I2C Initialization + */ + I2C_InitStruct.PeripheralMode = LL_I2C_MODE_I2C; + I2C_InitStruct.Timing = 0x30D29DE4; + I2C_InitStruct.AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE; + I2C_InitStruct.DigitalFilter = 0; + I2C_InitStruct.OwnAddress1 = 0; + I2C_InitStruct.TypeAcknowledge = LL_I2C_ACK; + I2C_InitStruct.OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT; + LL_I2C_Init(I2C2, &I2C_InitStruct); + LL_I2C_EnableAutoEndMode(I2C2); + LL_I2C_SetOwnAddress2(I2C2, 0, LL_I2C_OWNADDRESS2_NOMASK); + LL_I2C_DisableOwnAddress2(I2C2); + LL_I2C_DisableGeneralCall(I2C2); + LL_I2C_EnableClockStretching(I2C2); + /* USER CODE BEGIN I2C2_Init 2 */ + + /* USER CODE END I2C2_Init 2 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/G4FANCYCANTESTING/Core/Src/spi.c b/G4FANCYCANTESTING/Core/Src/spi.c new file mode 100644 index 000000000..66459f2ec --- /dev/null +++ b/G4FANCYCANTESTING/Core/Src/spi.c @@ -0,0 +1,95 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file spi.c + * @brief This file provides code for the configuration + * of the SPI instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "spi.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* SPI3 init function */ +void MX_SPI3_Init(void) +{ + + /* USER CODE BEGIN SPI3_Init 0 */ + + /* USER CODE END SPI3_Init 0 */ + + LL_SPI_InitTypeDef SPI_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI3); + + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC); + /**SPI3 GPIO Configuration + PC10 ------> SPI3_SCK + PC11 ------> SPI3_MISO + PC12 ------> SPI3_MOSI + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_6; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_6; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_12; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_6; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI3_Init 1 */ + + /* USER CODE END SPI3_Init 1 */ + SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX; + SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; + SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_4BIT; + SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW; + SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; + SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; + SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV32; + SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; + SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + SPI_InitStruct.CRCPoly = 7; + LL_SPI_Init(SPI3, &SPI_InitStruct); + LL_SPI_SetStandard(SPI3, LL_SPI_PROTOCOL_MOTOROLA); + LL_SPI_EnableNSSPulseMgt(SPI3); + /* USER CODE BEGIN SPI3_Init 2 */ + + /* USER CODE END SPI3_Init 2 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/G4FANCYCANTESTING/Core/Src/stm32g4xx_hal_msp.c b/G4FANCYCANTESTING/Core/Src/stm32g4xx_hal_msp.c new file mode 100644 index 000000000..69189ef4e --- /dev/null +++ b/G4FANCYCANTESTING/Core/Src/stm32g4xx_hal_msp.c @@ -0,0 +1,86 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g4xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral + */ + HAL_PWREx_DisableUCPDDeadBattery(); + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/G4FANCYCANTESTING/Core/Src/stm32g4xx_it.c b/G4FANCYCANTESTING/Core/Src/stm32g4xx_it.c new file mode 100644 index 000000000..dd322200e --- /dev/null +++ b/G4FANCYCANTESTING/Core/Src/stm32g4xx_it.c @@ -0,0 +1,194 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_it.h" + +#include "main.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +// extern FDCAN_HandleTypeDef hfdcan2; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) {} + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32G4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32g4xx.s). */ +/******************************************************************************/ diff --git a/G4FANCYCANTESTING/Core/Src/tim.c b/G4FANCYCANTESTING/Core/Src/tim.c new file mode 100644 index 000000000..7f521c3bf --- /dev/null +++ b/G4FANCYCANTESTING/Core/Src/tim.c @@ -0,0 +1,79 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.c + * @brief This file provides code for the configuration + * of the TIM instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "tim.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* TIM2 init function */ +void MX_TIM2_Init(void) +{ + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + LL_TIM_InitTypeDef TIM_InitStruct = {0}; + LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2); + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + TIM_InitStruct.Prescaler = 0; + TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct.Autoreload = 4294967295; + TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + LL_TIM_Init(TIM2, &TIM_InitStruct); + LL_TIM_DisableARRPreload(TIM2); + LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL); + TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_FORCED_ACTIVE; + TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct.CompareValue = 0; + TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH; + LL_TIM_OC_Init(TIM2, LL_TIM_CHANNEL_CH1, &TIM_OC_InitStruct); + LL_TIM_OC_DisableFast(TIM2, LL_TIM_CHANNEL_CH1); + LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET); + LL_TIM_DisableMasterSlaveMode(TIM2); + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); + /**TIM2 GPIO Configuration + PA0 ------> TIM2_CH1 + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_1; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/G4FANCYCANTESTING/Core/Src/usart.c b/G4FANCYCANTESTING/Core/Src/usart.c new file mode 100644 index 000000000..41561862c --- /dev/null +++ b/G4FANCYCANTESTING/Core/Src/usart.c @@ -0,0 +1,184 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.c + * @brief This file provides code for the configuration + * of the USART instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "usart.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* LPUART1 init function */ + +void MX_LPUART1_UART_Init(void) +{ + + /* USER CODE BEGIN LPUART1_Init 0 */ + + /* USER CODE END LPUART1_Init 0 */ + + LL_LPUART_InitTypeDef LPUART_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + LL_RCC_SetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE_HSI); + + /* Peripheral clock enable */ + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPUART1); + + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); + /**LPUART1 GPIO Configuration + PA2 ------> LPUART1_TX + PA3 ------> LPUART1_RX + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_2; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_12; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_3; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_12; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN LPUART1_Init 1 */ + + /* USER CODE END LPUART1_Init 1 */ + LPUART_InitStruct.PrescalerValue = LL_LPUART_PRESCALER_DIV1; + LPUART_InitStruct.BaudRate = 115200; + LPUART_InitStruct.DataWidth = LL_LPUART_DATAWIDTH_8B; + LPUART_InitStruct.StopBits = LL_LPUART_STOPBITS_1; + LPUART_InitStruct.Parity = LL_LPUART_PARITY_NONE; + LPUART_InitStruct.TransferDirection = LL_LPUART_DIRECTION_TX_RX; + LPUART_InitStruct.HardwareFlowControl = LL_LPUART_HWCONTROL_NONE; + LL_LPUART_Init(LPUART1, &LPUART_InitStruct); + LL_LPUART_SetTXFIFOThreshold(LPUART1, LL_LPUART_FIFOTHRESHOLD_1_8); + LL_LPUART_SetRXFIFOThreshold(LPUART1, LL_LPUART_FIFOTHRESHOLD_1_8); + LL_LPUART_DisableFIFO(LPUART1); + + /* USER CODE BEGIN WKUPType LPUART1 */ + + /* USER CODE END WKUPType LPUART1 */ + + LL_LPUART_Enable(LPUART1); + + /* Polling LPUART1 initialisation */ + while ((!(LL_LPUART_IsActiveFlag_TEACK(LPUART1))) || (!(LL_LPUART_IsActiveFlag_REACK(LPUART1)))) {} + /* USER CODE BEGIN LPUART1_Init 2 */ + + /* USER CODE END LPUART1_Init 2 */ +} +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + LL_USART_InitTypeDef USART_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + LL_RCC_SetUSARTClockSource(LL_RCC_USART1_CLKSOURCE_PCLK2); + + /* Peripheral clock enable */ + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1); + + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); + /**USART1 GPIO Configuration + PC5 ------> USART1_RX + PA11 ------> USART1_CTS + PA12 ------> USART1_RTS + PB6 ------> USART1_TX + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_5; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_7; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_7; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_12; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_7; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_7; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + USART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1; + USART_InitStruct.BaudRate = 115200; + USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; + USART_InitStruct.StopBits = LL_USART_STOPBITS_1; + USART_InitStruct.Parity = LL_USART_PARITY_NONE; + USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; + USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_RTS_CTS; + USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; + LL_USART_Init(USART1, &USART_InitStruct); + LL_USART_SetTXFIFOThreshold(USART1, LL_USART_FIFOTHRESHOLD_1_8); + LL_USART_SetRXFIFOThreshold(USART1, LL_USART_FIFOTHRESHOLD_1_8); + LL_USART_DisableFIFO(USART1); + LL_USART_ConfigAsyncMode(USART1); + + /* USER CODE BEGIN WKUPType USART1 */ + + /* USER CODE END WKUPType USART1 */ + + LL_USART_Enable(USART1); + + /* Polling USART1 initialisation */ + while ((!(LL_USART_IsActiveFlag_TEACK(USART1))) || (!(LL_USART_IsActiveFlag_REACK(USART1)))) {} + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Lib/FancyLayers-RENAME/GRCAN/Inc/GRCAN_FancyLayer.h b/Lib/FancyLayers-RENAME/GRCAN/Inc/GRCAN_FancyLayer.h new file mode 100644 index 000000000..f89740426 --- /dev/null +++ b/Lib/FancyLayers-RENAME/GRCAN/Inc/GRCAN_FancyLayer.h @@ -0,0 +1,27 @@ +#include +#include + +#include "GRCAN_BUS_ID.h" +#include "GRCAN_CUSTOM_ID.h" +#include "GRCAN_MSG_DATA.h" +#include "GRCAN_MSG_ID.h" +#include "GRCAN_NODE_ID.h" +#include "can.h" +#include "grcan_utils.h" + +#ifndef GRCAN_FANCYLAYER_H +#define GRCAN_FANCYLAYER_H + +typedef struct { + GRCAN_NODE_ID srcID; + GRCAN_NODE_ID destNode; + GRCAN_MSG_ID messageID; +} GRCAN_Fancy_ID; + +GRCAN_BusMode GRCAN_BusModeForBus(GRCAN_BUS_ID bus); +bool GRCAN_InitBus(GRCAN_BusConfig *bus_config); + +uint32_t GRCAN_Fancy_EncodeID(GRCAN_Fancy_ID *id); +void GRCAN_Fancy_DecodeID(GRCAN_Fancy_ID *id, uint32_t rawID); + +#endif diff --git a/Lib/FancyLayers-RENAME/GRCAN/Inc/grcan_utils.h b/Lib/FancyLayers-RENAME/GRCAN/Inc/grcan_utils.h new file mode 100644 index 000000000..82eaeb535 --- /dev/null +++ b/Lib/FancyLayers-RENAME/GRCAN/Inc/grcan_utils.h @@ -0,0 +1,114 @@ +#include + +#include "GRCAN_BUS_ID.h" +#include "GRCAN_CUSTOM_ID.h" +#include "GRCAN_MSG_DATA.h" +#include "GRCAN_MSG_ID.h" +#include "GRCAN_NODE_ID.h" +#include "can.h" + +#ifndef GRCAN_UTILS_H +#define GRCAN_UTILS_H + +typedef enum { + GRCAN_MODE_CLASSIC, + GRCAN_MODE_FD +} GRCAN_BusMode; + +typedef enum { + GRCAN_CLK_DIV1, + GRCAN_CLK_DIV2, + GRCAN_CLK_DIV4, + GRCAN_CLK_DIV8, + GRCAN_CLK_DIV16 +} GRCAN_ClockDivider; + +typedef enum { + GRCAN_FRAME_CLASSIC, + GRCAN_FRAME_FD_NO_BRS, // every FD CAN uses this right now + GRCAN_FRAME_FD_BRS +} GRCAN_FrameFormat; +typedef enum { + GRCAN_CLKSRC_PCLK1, + GRCAN_CLKSRC_PLL, + GRCAN_CLKSRC_HSE +} GRCAN_ClockSource; +typedef enum { + GRCAN_OPMODE_NORMAL, + GRCAN_OPMODE_RESTRICTED, + GRCAN_OPMODE_BUS_MONITORING, + GRCAN_OPMODE_INTERNAL_LOOPBACK, + GRCAN_OPMODE_EXTERNAL_LOOPBACK +} GRCAN_OperatingMode; +typedef struct { + uint32_t prescaler; + uint32_t sjw; + uint32_t seg1; + uint32_t seg2; +} GRCAN_BitTimingPhase; + +typedef struct { + GRCAN_BitTimingPhase nominal; + GRCAN_BitTimingPhase data; +} GRCAN_BitTiming; + +typedef struct { + GPIO_TypeDef *port; + uint32_t pin; + uint32_t alternate_function; +} GRCAN_PinConfig; + +typedef struct { + uint32_t id_type; + uint32_t filter_index; + uint32_t filter_type; + uint32_t filter_config; + uint32_t filter_id1; + uint32_t filter_id2; +} GRCAN_FilterConfig; + +typedef enum { + GRCAN_Feature_DISABLE = 0, + GRCAN_Feature_ENABLE = 1 +} GRCAN_FeatureState; + +typedef struct { + GRCAN_BUS_ID bus; + FDCAN_GlobalTypeDef *fdcan_instance; + + GRCAN_ClockSource clock_source; + GRCAN_ClockDivider clock_divider; + GRCAN_FrameFormat frame_format; + GRCAN_OperatingMode operating_mode; + + GRCAN_FeatureState auto_retransmission; + GRCAN_FeatureState transmit_pause; + GRCAN_FeatureState protocol_exception; + GRCAN_BitTiming bit_timing; + + uint32_t std_filters_nbr; + uint32_t ext_filters_nbr; + + GRCAN_PinConfig rx_pin; + GRCAN_PinConfig tx_pin; + + CAN_RXCallback rx_callback; + + uint32_t rx_interrupt_priority; + uint32_t tx_interrupt_priority; + uint32_t tx_buffer_length; + + GRCAN_FilterConfig *filter_config; +} GRCAN_BusConfig; + +uint32_t GRCAN_ToHAL_ClockSource(GRCAN_ClockSource src); +uint32_t GRCAN_ToHAL_ClockDivider(GRCAN_ClockDivider div); +uint32_t GRCAN_ToHAL_FrameFormat(GRCAN_FrameFormat fmt); +uint32_t GRCAN_ToHAL_OperatingMode(GRCAN_OperatingMode mode); +uint32_t GRCAN_ToHAL_FeatureState(GRCAN_FeatureState state); +GRCAN_BusMode GRCAN_BusModeForBus(GRCAN_BUS_ID bus); +CANHandle *GRCAN_GetHandle(GRCAN_BUS_ID bus); +uint32_t GRCAN_to_DLC(uint32_t size); +uint32_t DLC_to_GRCAN(uint32_t dlc); + +#endif diff --git a/Lib/FancyLayers-RENAME/GRCAN/Src/grcan_fancylayer.c b/Lib/FancyLayers-RENAME/GRCAN/Src/grcan_fancylayer.c new file mode 100644 index 000000000..7014d688b --- /dev/null +++ b/Lib/FancyLayers-RENAME/GRCAN/Src/grcan_fancylayer.c @@ -0,0 +1,510 @@ +#include "GRCAN_FancyLayer.h" + +#include +#include + +#include "Logomatic.h" +#include "grcan_utils.h" +#include "main.h" +// #include "stm32g4xx_hal_fdcan.h" +// #include "stm32g4xx_hal_gpio.h" + +static CANHandle *grcan_primary = NULL; +static CANHandle *grcan_data = NULL; +static CANHandle *grcan_testing = NULL; +static CANHandle *grcan_charging = NULL; + +// typedef struct { +// FDCAN_HandleTypeDef *hal_fdcanP; +// CircularBuffer *tx_buffer; +// uint32_t tx_buffer_length; + +// can change rx callback settings to custom callback, check message size and count errors +// CAN_RXCallback rx_callback; + +// // for release +// GPIO_TypeDef *rx_gpio; +// GPIO_TypeDef *tx_gpio; +// uint32_t Clock_Source; + +// // state +// bool init; +// bool started; + +// // error states +// } CANHandle; + +static GRCAN_NODE_ID grcan_local_node_id = ALL; + +void GRCAN_ApplyDefaults(GRCAN_BusConfig *bus_config); +bool GRCAN_ValidateBusConfig(GRCAN_BusConfig *bus_config); + +void GRCAN_Raw_Send_Classic(GRCAN_BUS_ID bus, uint32_t rawID, void *data, uint32_t size); +void GRCAN_Raw_Send_FD(GRCAN_BUS_ID bus, uint32_t rawID, void *data, uint32_t size); + +// typedef struct { +// FDCAN_HandleTypeDef *hal_fdcanP; +// CircularBuffer *tx_buffer; +// uint32_t tx_buffer_length; + +// CAN_RXCallback rx_callback; + +// // for release +// GPIO_TypeDef *rx_gpio; +// GPIO_TypeDef *tx_gpio; +// uint32_t Clock_Source; + +// // state +// bool init; +// bool started; + +// // error states +// } CANHandle; + +// static GR_OLD_NODE_ID grcan_local_node_id; + +// can change rx callback settings to custom callback, check message size and count errors + +/* +EXAMPLE USAGE: + +GRCAN_BusConfig ecu_primary_cfg = { + .bus = GR_OLD_BUS_PRIMARY, + .fdcan_instance = FDCAN1, + + .clock_source = GRCAN_CLKSRC_PCLK1, + .clock_divider = GRCAN_CLK_DIV1, + .frame_format = GRCAN_FRAME_FD_NO_BRS, + .operating_mode = GRCAN_OPMODE_NORMAL, + + .auto_retransmission = GRCAN_FEATURE_ENABLE, + .transmit_pause = GRCAN_FEATURE_DISABLE, + .protocol_exception = GRCAN_FEATURE_ENABLE, + + .bit_timing = { + .nominal = { + .prescaler = 1, + .sjw = 16, + .seg1 = 127, + .seg2 = 42 + }, + .data = { + .prescaler = 8, + .sjw = 16, + .seg1 = 15, + .seg2 = 5 + } + }, + + .std_filters_nbr = 0, + .ext_filters_nbr = 2, + + .rx_pin = { + .port = GPIOA, + .pin = GPIO_PIN_11, + .alternate_function = GPIO_AF9_FDCAN1 + }, + + .tx_pin = { + .port = GPIOA, + .pin = GPIO_PIN_12, + .alternate_function = GPIO_AF9_FDCAN1 + }, + + .rx_callback = Read_CAN, + .rx_interrupt_priority = 15, + .tx_interrupt_priority = 15, + .tx_buffer_length = 5, + + .filter_config_fn = ECU_PrimaryFilters +}; + +*/ + +CANHandle *GRCAN_GetHandle(GRCAN_BUS_ID bus) +{ + switch (bus) { + case GRCAN_BUS_PRIMARY: + return grcan_primary; + case GRCAN_BUS_DATA: + return grcan_data; + case GRCAN_BUS_TESTING: + return grcan_testing; + case GRCAN_BUS_CHARGER: + return grcan_charging; + default: + return NULL; + } +} + +// typedef struct { +// // can baud rate is set by fdcan prescaler and RCC clock configurations +// FDCAN_GlobalTypeDef *fdcan_instance; // Base address of FDCAN peripheral in memory (FDCAN1, FDCAN2, FDCAN3 macros) + +// FDCAN_InitTypeDef hal_fdcan_init; +// CAN_RXCallback rx_callback; +// uint32_t rx_interrupt_priority; +// uint32_t tx_interrupt_priority; + +// // Circular Buffer +// uint32_t tx_buffer_length; + +// GPIO_TypeDef *rx_gpio; // Instance name, like GPIOA, GPIOB, etc. +// GPIO_InitTypeDef init_rx_gpio; // GPIO Parameters - set correct Alternate Function, no pullup/pulldown, high/very_high frequency +// GPIO_TypeDef *tx_gpio; +// GPIO_InitTypeDef init_tx_gpio; + +// // additional parameters +// } CANConfig; + +bool GRCAN_InitBus(GRCAN_BusConfig *bus_config) +{ + CANConfig cfg = {0}; + CANHandle **slot = NULL; + CANHandle *handle = NULL; + + if (bus_config == NULL) { + LOGOMATIC("GRCAN_InitBus: NULL bus_config\n"); + return false; + } + + GRCAN_ApplyDefaults(bus_config); + + if (!GRCAN_ValidateBusConfig(bus_config)) { + LOGOMATIC("GRCAN_InitBus: invalid config for bus %d\n", bus_config->bus); + return false; + } + + can_set_clksource(GRCAN_ToHAL_ClockSource(bus_config->clock_source)); + + cfg.fdcan_instance = bus_config->fdcan_instance; + + cfg.hal_fdcan_init.ClockDivider = GRCAN_ToHAL_ClockDivider(bus_config->clock_divider); + cfg.hal_fdcan_init.FrameFormat = GRCAN_ToHAL_FrameFormat(bus_config->frame_format); + cfg.hal_fdcan_init.Mode = GRCAN_ToHAL_OperatingMode(bus_config->operating_mode); + + cfg.hal_fdcan_init.AutoRetransmission = GRCAN_ToHAL_FeatureState(bus_config->auto_retransmission); + cfg.hal_fdcan_init.TransmitPause = GRCAN_ToHAL_FeatureState(bus_config->transmit_pause); + cfg.hal_fdcan_init.ProtocolException = GRCAN_ToHAL_FeatureState(bus_config->protocol_exception); + + cfg.hal_fdcan_init.NominalPrescaler = bus_config->bit_timing.nominal.prescaler; + cfg.hal_fdcan_init.NominalSyncJumpWidth = bus_config->bit_timing.nominal.sjw; + cfg.hal_fdcan_init.NominalTimeSeg1 = bus_config->bit_timing.nominal.seg1; + cfg.hal_fdcan_init.NominalTimeSeg2 = bus_config->bit_timing.nominal.seg2; + + cfg.hal_fdcan_init.DataPrescaler = bus_config->bit_timing.data.prescaler; + cfg.hal_fdcan_init.DataSyncJumpWidth = bus_config->bit_timing.data.sjw; + cfg.hal_fdcan_init.DataTimeSeg1 = bus_config->bit_timing.data.seg1; + cfg.hal_fdcan_init.DataTimeSeg2 = bus_config->bit_timing.data.seg2; + + cfg.hal_fdcan_init.StdFiltersNbr = bus_config->std_filters_nbr; + cfg.hal_fdcan_init.ExtFiltersNbr = bus_config->ext_filters_nbr; + + cfg.rx_callback = bus_config->rx_callback; + cfg.rx_interrupt_priority = bus_config->rx_interrupt_priority; + cfg.tx_interrupt_priority = bus_config->tx_interrupt_priority; + // cfg.tx_buffer_length = bus_config->tx_buffer_length; + + cfg.rx_gpio = bus_config->rx_pin.port; + cfg.init_rx_gpio.Pin = bus_config->rx_pin.pin; + cfg.init_rx_gpio.Mode = GPIO_MODE_AF_PP; + cfg.init_rx_gpio.Pull = GPIO_NOPULL; + cfg.init_rx_gpio.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + cfg.init_rx_gpio.Alternate = bus_config->rx_pin.alternate_function; + + cfg.tx_gpio = bus_config->tx_pin.port; + cfg.init_tx_gpio.Pin = bus_config->tx_pin.pin; + cfg.init_tx_gpio.Mode = GPIO_MODE_AF_PP; + cfg.init_tx_gpio.Pull = GPIO_NOPULL; + cfg.init_tx_gpio.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + cfg.init_tx_gpio.Alternate = bus_config->tx_pin.alternate_function; + + switch (bus_config->bus) { + case GRCAN_BUS_PRIMARY: + slot = &grcan_primary; + break; + case GRCAN_BUS_DATA: + slot = &grcan_data; + break; + case GRCAN_BUS_TESTING: + slot = &grcan_testing; + break; + case GRCAN_BUS_CHARGER: + slot = &grcan_charging; + break; + default: + LOGOMATIC("GRCAN_InitBus: invalid bus %d\n", bus_config->bus); + return false; + } + + handle = can_init(&cfg); + if (handle == NULL) { + LOGOMATIC("GRCAN_InitBus: can_init failed for bus %d\n", bus_config->bus); + return false; + } + + *slot = handle; + + if (bus_config->filter_config != NULL) { + FDCAN_FilterTypeDef filter = { + .IdType = bus_config->filter_config->id_type, + .FilterIndex = bus_config->filter_config->filter_index, + .FilterType = bus_config->filter_config->filter_type, + .FilterConfig = bus_config->filter_config->filter_config, + .FilterID1 = bus_config->filter_config->filter_id1, + .FilterID2 = bus_config->filter_config->filter_id2, + }; + + if (HAL_FDCAN_ConfigFilter(handle->hal_fdcanP, &filter) != HAL_OK) { + LOGOMATIC("GRCAN_InitBus: filter config failed for bus %d\n", bus_config->bus); + return false; + } + } + + if (can_start(handle) != 0) { + LOGOMATIC("GRCAN_InitBus: can_start failed for bus %d\n", bus_config->bus); + return false; + } + + return true; +} + +// void GRCAN_Fancy_Init(GR_OLD_NODE_ID localID, CANHandle *primaryCAN, CANHandle *dataCAN, CANHandle *testingCAN, CANHandle *chargingCAN) +// { + +// grcan_local_node_id = localID; + +// if (primaryCAN == NULL) { +// LOGOMATIC("GRCAN_Fancy_Init: Received NULL pointer for primary CAN handle\n"); +// } + +// if (dataCAN == NULL) { +// LOGOMATIC("GRCAN_Fancy_Ini +// t: Received NULL pointer for data CAN handle\n"); +// } + +// if (testingCAN == NULL) { +// LOGOMATIC("GRCAN_Fancy_Init: Received NULL pointer for testing CAN handle\n"); +// } + +// if (chargingCAN == NULL) { +// LOGOMATIC("GRCAN_Fancy_Init: Received NULL pointer for charging CAN handle\n"); +// } + +// grcan_primary = primaryCAN; +// grcan_data = dataCAN; +// grcan_testing = testingCAN; +// grcan_charging = chargingCAN; +// } + +void GRCAN_SetLocalNodeID(GRCAN_NODE_ID localID) +{ + if (localID == ALL) { + LOGOMATIC("GRCAN_SetLocalNodeID: Local node ID cannot be GR_ALL\n"); + return; + } + + grcan_local_node_id = localID; +} + +uint32_t GRCAN_Fancy_EncodeID(GRCAN_Fancy_ID *id) +{ + if (id == NULL) { + LOGOMATIC("GRCAN_Fancy_Encode: Received NULL pointer\n"); + return 0; + } + + return ((0xFF & id->srcID) << 20) | ((0xFFF & id->messageID) << 8) | (0xFF & id->destNode); +} + +void GRCAN_Fancy_DecodeID(GRCAN_Fancy_ID *id, uint32_t rawID) +{ + if (id == NULL) { + LOGOMATIC("GRCAN_Fancy_Decode: Received NULL pointer\n"); + return; + } + + if ((rawID & ~0x0FFFFFFFU) != 0U) { + LOGOMATIC("GRCAN_Fancy_Decode: ID field sizes are too large\n"); + return; + } + + id->srcID = (rawID >> 20) & 0xFF; + id->destNode = rawID & 0xFF; + id->messageID = (rawID >> 8) & 0xFFF; + + if (id->srcID == ALL) { + LOGOMATIC("GRCAN_Fancy_Decode: Source ID cannot be GR_ALL\n"); + } + + if (id->destNode == ALL) { + LOGOMATIC("GRCAN_Fancy_Decode: Destination ID cannot be GR_ALL\n"); + } +} + +void GRCAN_Fancy_Send(GRCAN_BUS_ID bus, GRCAN_NODE_ID destNode, GRCAN_MSG_ID messageID, void *data, uint32_t size) +{ + GRCAN_Fancy_ID id = { + .srcID = grcan_local_node_id, + .destNode = destNode, + .messageID = messageID, + }; + + if (id.srcID == ALL) { + LOGOMATIC("GRCAN_Fancy_Send: Source ID cannot be GR_ALL\n"); + return; + } + + GRCAN_BusMode mode = GRCAN_BusModeForBus(bus); + if (mode == GRCAN_MODE_FD) { + GRCAN_Raw_Send_FD(bus, GRCAN_Fancy_EncodeID(&id), data, size); + return; + } else if (mode == GRCAN_MODE_CLASSIC) { + GRCAN_Raw_Send_Classic(bus, GRCAN_Fancy_EncodeID(&id), data, size); + return; + } else { + LOGOMATIC("GRCAN_Fancy_Send: invalid bus mode for bus %d\n", bus); + return; + } +} + +/* +identifier can be standard (11-bit) or extended (29-bit) +TxFrameType can be data or remote frame + data frame contains 0-8 bytes of data, RTR dominant (0) - send data + remote frame contains no data (still specify DLC), RTR recessive (1) - request data + RTR bit automatically encoded with FDCAN_REMOTE_FRAME and FDCAN_DATA_FRAME, no need to manually set it +ErrorStateIndicator can be active or passive +DataLength can be 0-8 bytes (classic CAN) and must be set to the number of bytes being sent +BitRateSwitch can be on or off, but we will always set it to off +TxEventFifoControl can be set to generate events on transmission +MessageMarker can be used to identify the message in the Tx event FIFO +*/ + +void GRCAN_Raw_Send_Classic(GRCAN_BUS_ID bus, uint32_t rawID, void *data, uint32_t size) +{ + if (size > 8) { + LOGOMATIC("GRCAN_Raw_Send_Classic: size %lu > 8 (classic CAN)\n", size); + return; + } + + if ((data == NULL) && (size > 0)) { + LOGOMATIC("GRCAN_Raw_Send_Classic: NULL data with nonzero size\n"); + return; + } + + if (GRCAN_BusModeForBus(bus) != GRCAN_MODE_CLASSIC) { + LOGOMATIC("GRCAN_Raw_Send_Classic: bus %d is not in classic mode\n", bus); + return; + } + + FDCAN_TxHeaderTypeDef header = { + .Identifier = rawID, + .IdType = FDCAN_EXTENDED_ID, // using extended ID -- src << 20 | msgID << 8 | dest + .TxFrameType = FDCAN_DATA_FRAME, // data frame + .ErrorStateIndicator = FDCAN_ESI_ACTIVE, + .DataLength = GRCAN_to_DLC(size), + .BitRateSwitch = FDCAN_BRS_OFF, + .TxEventFifoControl = FDCAN_NO_TX_EVENTS, + .MessageMarker = 0, + }; + + FDCANTxMessage msg = {0}; + msg.tx_header = header; + // memcpy(&(msg.data), data, size); + memcpy(msg.data, data, size); + + CANHandle *handle = GRCAN_GetHandle(bus); + + if (!handle) { + LOGOMATIC("GRCAN_Raw_Send_Classic: bus %d not configured\n", bus); + return; + } + + can_send(handle, &msg); + // switch (bus) { + // case GR_OLD_BUS_PRIMARY: + // if (!grcan_primary) { LOGOMATIC("ERROR: Primary CAN not configured. Primary Should use FDCAN:\n"); return; } + // can_send(grcan_primary, &msg); + // break; + // case GR_OLD_BUS_DATA: + // if (!grcan_data) { LOGOMATIC("Data CAN not configured\n"); return; } + // can_send(grcan_data, &msg); + // break; + // case GR_OLD_BUS_TESTING: + // if (!grcan_testing) { LOGOMATIC("ERROR: Testing CAN not configured. Testing Should use FDCAN:\n"); return; } + // can_send(grcan_testing, &msg); + // break; + // case GR_OLD_BUS_CHARGING: + // if (!grcan_charging) { LOGOMATIC("Charging CAN not configured\n"); return; } + // can_send(grcan_charging, &msg); + // break; + // default: + // LOGOMATIC("GRCAN_Raw_Send_Classic: Invalid bus ID %d\n", bus); + // break; + // } +} + +void GRCAN_Raw_Send_FD(GRCAN_BUS_ID bus, uint32_t rawID, void *data, uint32_t size) // FDCAN funciton allows for modification with different settings +{ + if (size > 64) { + LOGOMATIC("GRCAN_Raw_Send_FD: size %lu > 64 (CAN FD)\n", size); + return; + } + + if ((data == NULL) && (size > 0)) { + LOGOMATIC("GRCAN_Raw_Send_FD: NULL data with nonzero size\n"); + return; + } + + if (GRCAN_BusModeForBus(bus) != GRCAN_MODE_FD) { + LOGOMATIC("GRCAN_Raw_Send_FD: bus %d is not in FD mode\n", bus); + return; + } + + FDCAN_TxHeaderTypeDef header = { + .Identifier = rawID, + .IdType = FDCAN_EXTENDED_ID, // using extended ID -- src << 20 | msgID << 8 | dest + .TxFrameType = FDCAN_DATA_FRAME, // data frame + .ErrorStateIndicator = FDCAN_ESI_ACTIVE, + .DataLength = GRCAN_to_DLC(size), + .BitRateSwitch = FDCAN_BRS_OFF, + .TxEventFifoControl = FDCAN_NO_TX_EVENTS, + .MessageMarker = 0, + }; + + FDCANTxMessage msg = {0}; + msg.tx_header = header; + // memcpy(&(msg.data), data, size); + memcpy(msg.data, data, size); + + CANHandle *handle = GRCAN_GetHandle(bus); + + if (!handle) { + LOGOMATIC("GRCAN_Raw_Send_FD: bus %d not configured\n", bus); + return; + } + + can_send(handle, &msg); + // switch (bus) { + // case GR_OLD_BUS_PRIMARY: + // if (!grcan_primary) { LOGOMATIC("Primary CAN not configured\n"); return; } + // can_send(grcan_primary, &msg); + // break; + // case GR_OLD_BUS_DATA: + // if (!grcan_data) { LOGOMATIC("ERROR: Data CAN not configured. Data Should use FDCAN:\n"); return; } + // can_send(grcan_data, &msg); + // break; + // case GR_OLD_BUS_TESTING: + // if (!grcan_testing) { LOGOMATIC("Testing CAN not configured\n"); return; } + // can_send(grcan_testing, &msg); + // break; + // case GR_OLD_BUS_CHARGING: + // if (!grcan_charging) { LOGOMATIC("ERROR: Charging CAN not configured. Charging Should use FDCAN:\n"); return; } + // can_send(grcan_charging, &msg); + // break; + // default: + // LOGOMATIC("GRCAN_Raw_Send_FD: Invalid bus ID %d\n", bus); + // break; + // } +} diff --git a/Lib/FancyLayers-RENAME/GRCAN/Src/grcan_utils.c b/Lib/FancyLayers-RENAME/GRCAN/Src/grcan_utils.c new file mode 100644 index 000000000..a68360465 --- /dev/null +++ b/Lib/FancyLayers-RENAME/GRCAN/Src/grcan_utils.c @@ -0,0 +1,228 @@ +#include "grcan_utils.h" + +#include +#include + +#include "GRCAN_FancyLayer.h" +#include "Logomatic.h" +#include "main.h" + +GRCAN_BusMode GRCAN_BusModeForBus(GRCAN_BUS_ID bus) +{ + switch (bus) { + case GRCAN_BUS_PRIMARY: + return GRCAN_MODE_FD; + case GRCAN_BUS_TESTING: + return GRCAN_MODE_FD; + case GRCAN_BUS_DATA: + return GRCAN_MODE_CLASSIC; + case GRCAN_BUS_CHARGER: + return GRCAN_MODE_CLASSIC; // update later + default: + LOGOMATIC("GRCAN_BusModeForBus: unknown bus %d\n", bus); + return GRCAN_MODE_CLASSIC; + } +} + +uint32_t GRCAN_ToHAL_ClockSource(GRCAN_ClockSource src) +{ + switch (src) { + case GRCAN_CLKSRC_PCLK1: + return LL_RCC_FDCAN_CLKSOURCE_PCLK1; + case GRCAN_CLKSRC_PLL: + return LL_RCC_FDCAN_CLKSOURCE_PLL; + case GRCAN_CLKSRC_HSE: + return LL_RCC_FDCAN_CLKSOURCE_HSE; + default: + LOGOMATIC("GRCAN_ToHAL_ClockSource: default source %d, defaulting to PCLK1\n", src); + return LL_RCC_FDCAN_CLKSOURCE_PCLK1; + } +} + +uint32_t GRCAN_ToHAL_ClockDivider(GRCAN_ClockDivider div) +{ + switch (div) { + case GRCAN_CLK_DIV1: + return FDCAN_CLOCK_DIV1; + case GRCAN_CLK_DIV2: + return FDCAN_CLOCK_DIV2; + case GRCAN_CLK_DIV4: + return FDCAN_CLOCK_DIV4; + case GRCAN_CLK_DIV8: + return FDCAN_CLOCK_DIV8; + case GRCAN_CLK_DIV16: + return FDCAN_CLOCK_DIV16; + default: + LOGOMATIC("GRCAN_ToHAL_ClockDivider: default divider %d, defaulting to DIV1\n", div); + return FDCAN_CLOCK_DIV1; + } +} + +uint32_t GRCAN_ToHAL_FrameFormat(GRCAN_FrameFormat fmt) +{ + switch (fmt) { + case GRCAN_FRAME_CLASSIC: + return FDCAN_FRAME_CLASSIC; + case GRCAN_FRAME_FD_NO_BRS: + return FDCAN_FRAME_FD_NO_BRS; + case GRCAN_FRAME_FD_BRS: + return FDCAN_FRAME_FD_BRS; + default: + LOGOMATIC("GRCAN_ToHAL_FrameFormat: default frame format %d, defaulting to FD_NO_BRS\n", fmt); + return FDCAN_FRAME_FD_NO_BRS; + } +} + +uint32_t GRCAN_ToHAL_OperatingMode(GRCAN_OperatingMode mode) +{ + switch (mode) { + case GRCAN_OPMODE_NORMAL: + return FDCAN_MODE_NORMAL; + case GRCAN_OPMODE_RESTRICTED: + return FDCAN_MODE_RESTRICTED_OPERATION; + case GRCAN_OPMODE_BUS_MONITORING: + return FDCAN_MODE_BUS_MONITORING; + case GRCAN_OPMODE_INTERNAL_LOOPBACK: + return FDCAN_MODE_INTERNAL_LOOPBACK; + case GRCAN_OPMODE_EXTERNAL_LOOPBACK: + return FDCAN_MODE_EXTERNAL_LOOPBACK; + default: + LOGOMATIC("GRCAN_ToHAL_OperatingMode: default mode %d, defaulting to NORMAL\n", mode); + return FDCAN_MODE_NORMAL; + } + + // internal loopback for testing +} + +static void GRCAN_SetDefaultBitTiming(GRCAN_BitTiming *timing) +{ + if (timing == NULL) { + LOGOMATIC("GRCAN_SetDefaultBitTiming: NULL timing pointer\n"); + return; + } + + timing->nominal.prescaler = 1; + timing->nominal.sjw = 16; + timing->nominal.seg1 = 127; + timing->nominal.seg2 = 42; + + timing->data.prescaler = 8; + timing->data.sjw = 16; + timing->data.seg1 = 15; + timing->data.seg2 = 5; +} + +void GRCAN_SetDefaultBusConfig(GRCAN_BusConfig *busCfg, GRCAN_BUS_ID bus) +{ + if (busCfg == NULL) { + LOGOMATIC("GRCAN_SetDefaultBusConfig: NULL busCfg pointer\n"); + return; + } + + memset(busCfg, 0, sizeof(*busCfg)); + + busCfg->bus = bus; + + busCfg->clock_source = GRCAN_CLKSRC_PCLK1; + busCfg->clock_divider = GRCAN_CLK_DIV1; + busCfg->frame_format = GRCAN_FRAME_FD_NO_BRS; + busCfg->operating_mode = GRCAN_OPMODE_NORMAL; + + busCfg->auto_retransmission = GRCAN_Feature_ENABLE; + busCfg->transmit_pause = GRCAN_Feature_DISABLE; + busCfg->protocol_exception = GRCAN_Feature_ENABLE; + + GRCAN_SetDefaultBitTiming(&busCfg->bit_timing); + + busCfg->std_filters_nbr = 1; + busCfg->ext_filters_nbr = 0; + + busCfg->rx_interrupt_priority = 15; + busCfg->tx_interrupt_priority = 15; + busCfg->tx_buffer_length = 5; + + busCfg->filter_config = NULL; +} + +uint32_t GRCAN_to_DLC(uint32_t size) +{ + switch (size) { + case 0: + return FDCAN_DLC_BYTES_0; + case 1: + return FDCAN_DLC_BYTES_1; + case 2: + return FDCAN_DLC_BYTES_2; + case 3: + return FDCAN_DLC_BYTES_3; + case 4: + return FDCAN_DLC_BYTES_4; + case 5: + return FDCAN_DLC_BYTES_5; + case 6: + return FDCAN_DLC_BYTES_6; + case 7: + return FDCAN_DLC_BYTES_7; + case 8: + return FDCAN_DLC_BYTES_8; + case 12: + return FDCAN_DLC_BYTES_12; + case 16: + return FDCAN_DLC_BYTES_16; + case 20: + return FDCAN_DLC_BYTES_20; + case 24: + return FDCAN_DLC_BYTES_24; + case 32: + return FDCAN_DLC_BYTES_32; + case 48: + return FDCAN_DLC_BYTES_48; + case 64: + return FDCAN_DLC_BYTES_64; + + default: + LOGOMATIC("Invalid CAN FD size: %lu\n, defaulting to 8 \n", size); + return FDCAN_DLC_BYTES_8; + } +} + +uint32_t DLC_to_GRCAN(uint32_t dlc) +{ + switch (dlc) { + case FDCAN_DLC_BYTES_0: + return 0; + case FDCAN_DLC_BYTES_1: + return 1; + case FDCAN_DLC_BYTES_2: + return 2; + case FDCAN_DLC_BYTES_3: + return 3; + case FDCAN_DLC_BYTES_4: + return 4; + case FDCAN_DLC_BYTES_5: + return 5; + case FDCAN_DLC_BYTES_6: + return 6; + case FDCAN_DLC_BYTES_7: + return 7; + case FDCAN_DLC_BYTES_8: + return 8; + case FDCAN_DLC_BYTES_12: + return 12; + case FDCAN_DLC_BYTES_16: + return 16; + case FDCAN_DLC_BYTES_20: + return 20; + case FDCAN_DLC_BYTES_24: + return 24; + case FDCAN_DLC_BYTES_32: + return 32; + case FDCAN_DLC_BYTES_48: + return 48; + case FDCAN_DLC_BYTES_64: + return 64; + default: + LOGOMATIC("Invalid CAN FD DLC code: %lu\n, defaulting to 8 \n", dlc); + return 8; + } +} diff --git a/Lib/FancyLayers-RENAME/GRCAN/grcan_fancylayer.cmake b/Lib/FancyLayers-RENAME/GRCAN/grcan_fancylayer.cmake new file mode 100644 index 000000000..650437610 --- /dev/null +++ b/Lib/FancyLayers-RENAME/GRCAN/grcan_fancylayer.cmake @@ -0,0 +1,62 @@ +add_library(GRCAN_FANCYLAYER INTERFACE) + +target_include_directories( + GRCAN_FANCYLAYER + INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/Inc + #${CMAKE_CURRENT_LIST_DIR}/TemporaryHoldover/Inc + #${Project_SOURCE_DIR}/Autogen/CAN//Inc + #${PROJECT_SOURCE_DIR}/Lib/Peripherals/CAN/Inc + #${PROJECT_SOURCE_DIR}/Lib/Utils/CircularBuffer/Inc +) + +target_sources( + GRCAN_FANCYLAYER + INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/Src/grcan_fancylayer.c + ${CMAKE_CURRENT_LIST_DIR}/Src/grcan_utils.c +) + +target_link_libraries( + GRCAN_FANCYLAYER + INTERFACE + GLOBALSHARE_LIB + CANfigurator + CircularBuffer_Lib + PERIPHERAL_CAN_LIB + GR_OLD_CAN_MESSAGES + STM32_HAL_LL_G4xx + #GRCAN_LIB #maybe add back +) + +if(CMAKE_PRESET_NAME STREQUAL "HOOTLTest") + # target_compile_definitions(LOGOMATIC_LIB INTERFACE LOGOMATIC_ENABLED) + + # add_executable(logomatic_simple) + # target_sources( + # logomatic_simple + # PRIVATE + # ${CMAKE_CURRENT_LIST_DIR}/Test/Src/logomatic_simple_print.c + # ) + # target_include_directories( + # logomatic_simple + # PRIVATE + # ${CMAKE_CURRENT_LIST_DIR}/Test/Inc + # ) + # target_link_libraries(logomatic_simple PRIVATE LOGOMATIC_LIB) + # add_test(logomatic_simple_test logomatic_simple) + + # add_executable(logomatic_float) + # target_sources( + # logomatic_float + # PRIVATE + # ${CMAKE_CURRENT_LIST_DIR}/Test/Src/logomatic_float_print.c + # ) + # target_include_directories( + # logomatic_float + # PRIVATE + # ${CMAKE_CURRENT_LIST_DIR}/Test/Inc + # ) + # target_link_libraries(logomatic_float PRIVATE LOGOMATIC_LIB) + # add_test(logomatic_float_test logomatic_float) +endif()